公开(公告)号：US20200233814A1

公开(公告)日：2020-07-23

申请号：US16786815

申请日：2020-02-10

Applicant: Intel Corporation

Inventor： Farah E. FARGO ,  Mitchell DIAMOND ,  David KEPPEL ,  Samantika S. SURY ,  Binh PHAM ,  Shobha VISSAPRAGADA

IPC: G06F12/1027

Abstract: Examples described herein relate to a computing system supporting custom page sized ranges for an application to map contiguous memory regions instead of many smaller sized pages. An application can request a custom range size. An operating system can allocate a contiguous physical memory region to a virtual address range by specifying a custom range sizes that are larger or smaller than the normal general page sizes. Virtual-to-physical address translation can occur using an address range circuitry and translation lookaside buffer in parallel. The address range circuitry can determine if a custom entry is available to use to identify a physical address translation for the virtual address. Physical address translation can be performed by transforming the virtual address in some examples.

公开(公告)号：US20220201103A1

公开(公告)日：2022-06-23

申请号：US17691003

申请日：2022-03-09

Applicant: Intel Corporation

Inventor： David KEPPEL ,  Chitra NATARAJAN ,  Venkata KRISHNAN

IPC: H04L69/22 ,  H04L49/9057 ,  H04L49/90

Abstract: Examples described herein relate to coalescing one or more messages into a coalesced message and representing one or more fields of the metadata of the one or more messages using one or more codes, wherein at least one of the one or more codes uses fewer bits than that of original metadata fields to compact the metadata fields. In some examples, the metadata includes at least one or more of: a target processing element (PE) number or identifier, message length, operation to perform, target address where to read or write data, source PE number or identifier, initiator address in which to write result data, or message identifier.

公开(公告)号：US20220107897A1

公开(公告)日：2022-04-07

申请号：US17552239

申请日：2021-12-15

Applicant: Intel Corporation

Inventor： David KEPPEL ,  Swapna RAJ ,  Kermin CHOFLEMING ,  Samantika S. SURY

IPC: G06F12/0842

Abstract: Examples described herein relate to circuitry to selectively disable cache snoop operations issued by a particular processor or its cache manager based on data in a memory address range, to be accessed by the particular processor, having been flushed from one or more other cache devices accessible to other processors. At or after completion of flushing or scrubbing data in the memory address range to memory, the particular processor or its cache manager do not issue snoop operations for accesses to the memory address range. In response to an access by some other device to the memory address range, the processor or cache manager may resume issuing snoop operations.

公开(公告)号：US20220011966A1

公开(公告)日：2022-01-13

申请号：US17485114

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： David KEPPEL ,  David M. OZOG

IPC: G06F3/06

Abstract: Methods and apparatus for reduced network load with receiver-managed offset (RMO) PUT or GET messages. An RMO PUT message including an RMO key, data, and a length is sent from an initiator to a target, where the RMO key is extracted by a Network Interface controller (NIC), SmartNIC, or Infrastructure Processing Unit and used to identify an address or address offset of a memory buffer in a target memory at which to write the data. An RMO GET message is sent from an initiator to a target and includes an RMO key, a source buffer on the target, and a length. The target processes the RMO GET, reads the length of data from its source buffer, and returns a message to the initiator including the RMO key, the read data, and the length. The RMO key is extracted and used to identify an address or address offset of a memory buffer in a memory on the initiator in which to write the read data.