公开(公告)号：US20170237797A1

公开(公告)日：2017-08-17

申请号：US15384294

申请日：2016-12-19

Applicant: Intel Corporation

Inventor： Bharath Muthiah ,  William Rash ,  Glenn Hinton ,  Martin G. Dixon ,  Scott Hahn ,  David Papworth

IPC: H04L29/06

Abstract: In one embodiment, Quality of Service (QoS) criteria based server side binary translation and execution of applications is performed on multiple servers utilizing distributed translation and execution in either a virtualized or native execution environment. The translated applications are executed to generate output display data, the output display data is encoded in a media format suitable for video streaming, and the video stream is delivered over a network to a client device. In one embodiment, one or more graphics processors assist the central processors of the servers by accelerating the rendering of the application output, and a media encoder encodes the application output into a media format.

公开(公告)号：US11294809B2

公开(公告)日：2022-04-05

申请号：US16115067

申请日：2018-08-28

Applicant: Intel Corporation

Inventor： Jason W. Brandt ,  Robert S. Chappell ,  Jesus Corbal ,  Edward T. Grochowski ,  Stephen H. Gunther ,  Buford M. Guy ,  Thomas R. Huff ,  Christopher J. Hughes ,  Elmoustapha Ould-Ahmed-Vall ,  Ronak Singhal ,  Seyed Yahya Sotoudeh ,  Bret L. Toll ,  Lihu Rappoport ,  David Papworth ,  James D. Allen

IPC: G06F12/0831 ,  G06F12/1027 ,  G06F12/1009 ,  G06F9/30

Abstract: Embodiments of an invention a processor architecture are disclosed. In an embodiment, a processor includes a decoder, an execution unit, a coherent cache, and an interconnect. The decoder is to decode an instruction to zero a cache line. The execution unit is to issue a write command to initiate a cache line sized write of zeros. The coherent cache is to receive the write command, to determine whether there is a hit in the coherent cache and whether a cache coherency protocol state of the hit cache line is a modified state or an exclusive state, to configure a cache line to indicate all zeros, and to issue the write command toward the interconnect. The interconnect is to, responsive to receipt of the write command, issue a snoop to each of a plurality of other coherent caches for which it must be determined if there is a hit.

公开(公告)号：US20190012266A1

公开(公告)日：2019-01-10

申请号：US16115067

申请日：2018-08-28

Applicant: Intel Corporation

Inventor： Jason W. Brandt ,  Robert S. Chappell ,  Jesus Corbal ,  Edward T. Grochowski ,  Stephen H. Gunther ,  Buford M. Guy ,  Thomas R. Huff ,  Christopher J. Hughes ,  Elmoustapha Ould-Ahmed-Vall ,  Ronak Singhal ,  Seyed Yahya Sotoudeh ,  Bret L. Toll ,  Lihu Rappoport ,  David Papworth ,  James D. Allen

IPC: G06F12/0831 ,  G06F12/1027 ,  G06F12/1009

Abstract: Embodiments of an invention a processor architecture are disclosed. In an embodiment, a processor includes a decoder, an execution unit, a coherent cache, and an interconnect. The decoder is to decode an instruction to zero a cache line. The execution unit is to issue a write command to initiate a cache line sized write of zeros. The coherent cache is to receive the write command, to determine whether there is a hit in the coherent cache and whether a cache coherency protocol state of the hit cache line is a modified state or an exclusive state, to configure a cache line to indicate all zeros, and to issue the write command toward the interconnect. The interconnect is to, responsive to receipt of the write command, issue a snoop to each of a plurality of other coherent caches for which it must be determined if there is a hit.

公开(公告)号：US20180165199A1

公开(公告)日：2018-06-14

申请号：US15376647

申请日：2016-12-12

Applicant: Intel Corporation

Inventor： Jason W. Brandt ,  Robert S. Chappell ,  Jesus Corbal ,  Edward T. Grochowski ,  Stephen H. Gunther ,  Buford M. Guy ,  Thomas R. Huff ,  Christopher J. Hughes ,  Elmoustapha Ould-Ahmed-Vall ,  Ronak Singhal ,  Seyed Yahya Sotoudeh ,  Bret L. Toll ,  Lihu Rappoport ,  David Papworth ,  James D. Allen

IPC: G06F12/0831 ,  G06F12/1027 ,  G06F12/1009

CPC classification number: G06F12/0831 ,  G06F12/1009 ,  G06F12/1027 ,  G06F2212/1016 ,  G06F2212/621 ,  G06F2212/68

Abstract: Embodiments of an invention a processor architecture are disclosed. In an embodiment, a processor includes a decoder, an execution unit, a coherent cache, and an interconnect. The decoder is to decode an instruction to zero a cache line. The execution unit is to issue a write command to initiate a cache line sized write of zeros. The coherent cache is to receive the write command, to determine whether there is a hit in the coherent cache and whether a cache coherency protocol state of the hit cache line is a modified state or an exclusive state, to configure a cache line to indicate all zeros, and to issue the write command toward the interconnect. The interconnect is to, responsive to receipt of the write command, issue a snoop to each of a plurality of other coherent caches for which it must be determined if there is a hit.

公开(公告)号：US10469557B2

公开(公告)日：2019-11-05

申请号：US15384294

申请日：2016-12-19

Applicant: Intel Corporation

Inventor： Bharath Muthiah ,  William Rash ,  Glenn Hinton ,  Martin G. Dixon ,  Scott Hahn ,  David Papworth

IPC: H04L29/06

Abstract: In one embodiment, Quality of Service (QoS) criteria based server side binary translation and execution of applications is performed on multiple servers utilizing distributed translation and execution in either a virtualized or native execution environment. The translated applications are executed to generate output display data, the output display data is encoded in a media format suitable for video streaming, and the video stream is delivered over a network to a client device. In one embodiment, one or more graphics processors assist the central processors of the servers by accelerating the rendering of the application output, and a media encoder encodes the application output into a media format.

公开(公告)号：US10282296B2

公开(公告)日：2019-05-07

申请号：US15376647

申请日：2016-12-12

Applicant: Intel Corporation

Inventor： Jason W. Brandt ,  Robert S. Chappell ,  Jesus Corbal ,  Edward T. Grochowski ,  Stephen H. Gunther ,  Buford M. Guy ,  Thomas R. Huff ,  Elmoustapha Ould-Ahmed-Vall ,  Bret L. Toll ,  David Papworth ,  James D. Allen

IPC: G06F12/0831 ,  G06F12/1009 ,  G06F12/1027

Abstract: Embodiments of an invention a processor architecture are disclosed. In an embodiment, a processor includes a decoder, an execution unit, a coherent cache, and an interconnect. The decoder is to decode an instruction to zero a cache line. The execution unit is to issue a write command to initiate a cache line sized write of zeros. The coherent cache is to receive the write command, to determine whether there is a hit in the coherent cache and whether a cache coherency protocol state of the hit cache line is a modified state or an exclusive state, to configure a cache line to indicate all zeros, and to issue the write command toward the interconnect. The interconnect is to, responsive to receipt of the write command, issue a snoop to each of a plurality of other coherent caches for which it must be determined if there is a hit.

公开(公告)号：US09525586B2

公开(公告)日：2016-12-20

申请号：US13844086

申请日：2013-03-15

Applicant: Intel Corporation

Inventor： Bharath Muthiah ,  William Bill Rash ,  Glenn Hinton ,  Martin G. Dixon ,  Scott Hayn ,  David Papworth

IPC: H04L29/06

CPC classification number: H04L65/80 ,  H04L29/0651 ,  H04L65/4084 ,  H04L65/607 ,  H04L67/42

Abstract: In one embodiment, Quality of Service (QoS) criteria based server side binary translation and execution of applications is performed on multiple servers utilizing distributed translation and execution in either a virtualized or native execution environment. The translated applications are executed to generate output display data, the output display data is encoded in a media format suitable for video streaming, and the video stream is delivered over a network to a client device. In one embodiment, one or more graphics processors assist the central processors of the servers by accelerating the rendering of the application output, and a media encoder encodes the application output into a media format.

Abstract translation: 在一个实施例中，基于服务器端的二进制翻译和应用的执行在多个服务器上利用在虚拟或本地执行环境中的分布式转换和执行来执行。 执行翻译的应用程序以产生输出显示数据，输出显示数据以适合于视频流的媒体格式进行编码，并且视频流通过网络传送到客户端设备。 在一个实施例中，一个或多个图形处理器通过加速应用输出的渲染来帮助服务器的中央处理器，并且媒体编码器将应用输出编码为媒体格式。