公开(公告)号：US20250126044A1

公开(公告)日：2025-04-17

申请号：US18981161

申请日：2024-12-13

Applicant: Intel Corporation

Inventor： Kartik LAKHOTIA ,  Hossein FARROKHBAKHT ,  Gurpreet Singh KALSI ,  Fabrizio PETRINI

IPC: H04L45/02 ,  H04L45/00

Abstract: Examples described herein relate to performing source routing of a packet to route the packet from a source to a destination through multiple routers by specification of a path of logical port identifiers through the multiple routers. In some examples, multiple routers are to translate the logical port identifiers into physical ports based on configurations. In some examples, the path of the packet through the multiple routers is based on a topology of the routers.

公开(公告)号：US20250119393A1

公开(公告)日：2025-04-10

申请号：US18980838

申请日：2024-12-13

Applicant: Intel Corporation

Inventor： Hossein FARROKHBAKHT ,  Fabrizio PETRINI

IPC: H04L49/253 ,  H04L49/112

Abstract: Examples described herein relate to switch circuitry that is to: based on receipt of a packet at the first input port and based on allocation of a first memory region in the memory to the first input port: based on capability of a first buffer for the first output port to store the packet, store the packet into the first buffer and egress the packet from the first buffer to the first output port and based on incapability of the first buffer to store the packet, store the packet into the first memory region and associate the packet with the first buffer prior to egress from the first output port.

公开(公告)号：US20240129260A1

公开(公告)日：2024-04-18

申请号：US18391540

申请日：2023-12-20

Applicant: Intel Corporation

Inventor： Hossein FARROKHBAKHT ,  Fabrizio PETRINI

IPC: H04L49/90 ,  G06F12/0802

CPC classification number: H04L49/90 ,  G06F12/0802 ,  G06F2212/60

Abstract: Examples described herein relate to a router. In some examples, the router includes an interface and circuitry coupled to the interface. In some examples, the circuitry is to reserve a memory region in a buffer for a response sent by a receiver of a forwarded packet.

公开(公告)号：US20210406214A1

公开(公告)日：2021-12-30

申请号：US17469644

申请日：2021-09-08

Applicant: Intel Corporation

Inventor： Fabrizio PETRINI ,  Kartik LAKHOTIA

IPC: G06F15/173 ,  G06F16/901

Abstract: Methods and apparatus for in-network parallel prefix scan. In one aspect, a dual binary tree topology is embedded in a network to compute prefix scan calculations as data packets traverse the binary tree topology. The dual binary tree topology includes up and down aggregation trees. Input values for a prefix scan are provided at leaves of the up tree. Prefix scan operations such as sum, multiplication, max, etc. are performed at aggregation nodes within the up tree as packets containing associated data propagate from the leaves to the root of the up tree. Output from aggregation nodes in the up tree are provide as input to aggregation nodes in the down tree. In the down tree, the packets containing associated data propagate from the root to its leaves. Output values for the prefix scan are provided at the leaves of the down tree.

公开(公告)号：US20250119384A1

公开(公告)日：2025-04-10

申请号：US18981356

申请日：2024-12-13

Applicant: Intel Corporation

Inventor： Hossein FARROKHBAKHT ,  Kartik LAKHOTIA ,  Gurpreet Singh KALSI ,  Fabrizio PETRINI

IPC: H04L47/24 ,  H04L47/12 ,  H04L47/26

Abstract: Examples described herein relate to a switch or router. In some examples, the switch or router is to: based on receipt of a control packet associated with a first link, store the control packet into a first region of memory associated with the first link; based on receipt of a data packet associated with the first link, store the data packet into a second region of memory associated with the first link; based on the control packet and data packet to egress from a same output port, insert a strict subset of content of the control packet into the data packet to form a second data packet; and cause transmission of the second data packet to a device from the output port.

公开(公告)号：US20240163221A1

公开(公告)日：2024-05-16

申请号：US18391579

申请日：2023-12-20

Applicant: Intel Corporation

Inventor： Hossein FARROKHBAKHT ,  Fabrizio PETRINI

IPC: H04L47/32 ,  H04L49/109

CPC classification number: H04L47/32 ,  H04L49/109

Abstract: Examples described herein relate to a router. In some examples, the router includes an interface and circuitry coupled to the interface. In some examples, the circuitry is to: based on detection of a drop of a packet of a flow: drop subsequently received packets of the flow and based on receipt of a packet associated with the dropped packet of the flow, forward the received packet and subsequent received packets of the flow.

公开(公告)号：US20250112698A1

公开(公告)日：2025-04-03

申请号：US18981500

申请日：2024-12-14

Applicant: Intel Corporation

Inventor： Kartik LAKHOTIA ,  Fabrizio PETRINI

IPC: H04B10/25 ,  H04Q11/00

Abstract: Examples described herein relate to a network configured according to a topology, where the network is to provide communication between the first computing device and the second computing device. In some examples, the network includes a combination of a connected shuffle box or a bipartite shuffle box. Various examples of connected shuffle boxes and bipartite shuffle boxes are described herein.

公开(公告)号：US20240129234A1

公开(公告)日：2024-04-18

申请号：US18391521

申请日：2023-12-20

Applicant: Intel Corporation

Inventor： Hossein FARROKHBAKHT ,  Fabrizio PETRINI

IPC: H04L47/11 ,  H04L45/24 ,  H04L47/129

CPC classification number: H04L47/11 ,  H04L45/24 ,  H04L47/129

Abstract: Examples described herein relate to a router interface device. In some examples, the router includes an interface and circuitry. In some examples, the circuitry is to: proactively drop a packet and send a negative acknowledgement (NACK) message to a sender based on lack of buffer space for a response associated with the packet and sent from a downstream network interface device that received the packet and also based on one or more of: congestion at a downstream switch or congestion at an endpoint receiver.

公开(公告)号：US20210149683A1

公开(公告)日：2021-05-20

申请号：US17129555

申请日：2020-12-21

Applicant: Intel Corporation

Inventor： Ankit MORE ,  Fabrizio PETRINI ,  Robert PAWLOWSKI ,  Shruti SHARMA ,  Sowmya PITCHAIMOORTHY

IPC: G06F9/4401 ,  G06F13/40

Abstract: Examples include techniques for an in-network acceleration of a parallel prefix-scan operation. Examples include configuring registers of a node included in a plurality of nodes on a same semiconductor package. The registers to be configured responsive to receiving an instruction that indicates a logical tree to map to a network topology that includes the node. The instruction associated with a prefix-scan operation to be executed by at least a portion of the plurality of nodes.

公开(公告)号：US20250112864A1

公开(公告)日：2025-04-03

申请号：US18980933

申请日：2024-12-13

Applicant: Intel Corporation

Inventor： Hossein FARROKHBAKHT ,  Kartik LAKHOTIA ,  Fabrizio PETRINI

IPC: H04L47/12 ,  H04L5/00 ,  H04L47/11 ,  H04L47/17

Abstract: Examples described herein relate to switch circuitry that is to: detect congestion based on information and based on detection of the congestion, perform a congestion mitigation action. In some examples, detect congestion based on the information includes: access a first value that indicates a number of packets received at a first input port and to be egressed from an output port of the multiple output ports, access a second value that indicates a number of packets received at a second input port and to be egressed from the output port, and generate the information based on the first value and the second value.