公开(公告)号：US20230034779A1

公开(公告)日：2023-02-02

申请号：US17963662

申请日：2022-10-11

Applicant: Intel Corporation

Inventor： Cunming LIANG ,  Jiayu HU ,  Jingjing WU ,  Qi FU ,  Zhirun YAN ,  Hongjun NI ,  Xiuchun LU ,  Fan ZHANG ,  Haiyue WANG ,  Pan ZHANG

IPC: G06F9/48 ,  G06F9/54

Abstract: Examples described herein relate to during runtime of at least one process, cause the one or more processors to execute the at least one process according to the determined thread model and in-process with a sidecar, wherein the sidecar is to communicate with a service mesh to communicate with one or more microservices of a cloud native application.

公开(公告)号：US20190205149A1

公开(公告)日：2019-07-04

申请号：US16299914

申请日：2019-03-12

Applicant: Intel Corporation

Inventor： Fan ZHANG ,  Bruce RICHARDSON

IPC: G06F9/455 ,  G06F12/1027 ,  G06F9/30

CPC classification number: G06F9/45545 ,  G06F9/30181 ,  G06F9/4555 ,  G06F12/1027

Abstract: Examples include a processor including fetch circuitry to fetch a guest physical address translation instruction having a format with fields to specify at least an opcode and locations of a source vector and a destination vector, decode circuitry to decode the fetched guest physical address translation instruction, and execution circuitry to execute the decoded guest physical address translation instruction. Execution of the decoded guest physical address translation instruction includes comparing guest physical addresses of the source vector with base and end addresses of a selected memory region, masking a guest physical address of the source vector if the guest physical address is in the selected memory region, translating the masked guest physical addresses into host addresses, and storing the host addresses into the destination vector.