公开(公告)号：US20230239244A1

公开(公告)日：2023-07-27

申请号：US18127881

申请日：2023-03-29

Applicant: Intel Corporation

Inventor： Ningbo TIAN ,  Xiahui YU ,  Kun QIU ,  Hao CHANG ,  Yong LIU ,  Hongjun NI

IPC: H04L47/11 ,  H04L47/122 ,  H04L43/062

CPC classification number: H04L47/11 ,  H04L47/122 ,  H04L43/062

Abstract: Examples described herein relate to a programmable packet processing pipeline configured to: access a data corresponding to multiple bins, respective bins associated with multiple packet flows and for respective bins: identify a single flow associated with a bin of the multiple bins as a candidate heavy hitter flow and determine a different packet flow as the candidate heavy hitter flow for the bin of the multiple bins.

公开(公告)号：US20230034779A1

公开(公告)日：2023-02-02

申请号：US17963662

申请日：2022-10-11

Applicant: Intel Corporation

Inventor： Cunming LIANG ,  Jiayu HU ,  Jingjing WU ,  Qi FU ,  Zhirun YAN ,  Hongjun NI ,  Xiuchun LU ,  Fan ZHANG ,  Haiyue WANG ,  Pan ZHANG

IPC: G06F9/48 ,  G06F9/54

Abstract: Examples described herein relate to during runtime of at least one process, cause the one or more processors to execute the at least one process according to the determined thread model and in-process with a sidecar, wherein the sidecar is to communicate with a service mesh to communicate with one or more microservices of a cloud native application.

公开(公告)号：US20240283756A1

公开(公告)日：2024-08-22

申请号：US18425968

申请日：2024-01-29

Applicant: Intel Corporation

Inventor： Shaopeng HE ,  Cunming LIANG ,  Jiang YU ,  Ziye YANG ,  Ping YU ,  Bo CUI ,  Jingjing WU ,  Liang MA ,  Hongjun NI ,  Zhiguo WEN ,  Changpeng LIU ,  Anjali Singhai JAIN ,  Daniel DALY ,  Yadong LI

IPC: H04L49/9057 ,  H04L1/1829 ,  H04L47/34 ,  H04L47/56 ,  H04L49/552 ,  H04L49/90

CPC classification number: H04L49/9057 ,  H04L1/1841 ,  H04L47/34 ,  H04L47/56 ,  H04L49/552 ,  H04L49/9094

Abstract: Examples described herein relate to offload reliable transport management to a network interface device and store packets to be resent, based on received packet receipt acknowledgements (ACKs), into one or more kernel space queues that are also accessible in user space.

公开(公告)号：US20200150734A1

公开(公告)日：2020-05-14

申请号：US16747202

申请日：2020-01-20

Applicant: Intel Corporation

Inventor： Liang MA ,  Weigang LI ,  Madhusudana RAGHUPATRUNI ,  Hongjun NI ,  Xuekun HU ,  Changzheng WEI ,  Chris MACNAMARA ,  John J. BROWNE

IPC: G06F1/324 ,  G06F21/60 ,  G06F9/54 ,  G06F21/53

Abstract: Examples described herein provide for a first core to map a measurement of packet processing activity and operating parameters so that a second core can access the measurement of packet processing activity and potentially modify an operating parameter of the first core. The second core can modify operating parameters of the first core based on the measurement of packet processing activity. The first and second cores can be provisioned on start-up with a common key. The first and second cores can use the common key to encrypt or decrypt measurement of packet processing activity and operating parameters that are shared between the first and second cores. Accordingly, operating parameters of the first core can be modified by a different core while providing for secure modification of operating parameters.

公开(公告)号：US20230053744A1

公开(公告)日：2023-02-23

申请号：US17981255

申请日：2022-11-04

Applicant: Intel Corporation

Inventor： Shaopeng HE ,  Cunming LIANG ,  Jiang YU ,  Ziye YANG ,  Ping YU ,  Bo CUI ,  Jingjing WU ,  Liang MA ,  Hongjun NI ,  Zhiguo WEN ,  Changpeng LIU ,  Anjali Singhai JAIN ,  Daniel DALY ,  Yadong LI

IPC: H04L49/9057 ,  H04L47/56 ,  H04L47/34 ,  H04L1/18 ,  H04L49/552

Abstract: Examples described herein relate to offload reliable transport management to a network interface device and store packets to be resent, based on received packet receipt acknowledgements (ACKs), into one or more kernel space queues that are also accessible in user space.

公开(公告)号：US20220247696A1

公开(公告)日：2022-08-04

申请号：US17238893

申请日：2021-04-23

Applicant: Intel Corporation

Inventor： Shaopeng HE ,  Cunming LIANG ,  Jiang YU ,  Ziye YANG ,  Ping YU ,  Bo CUI ,  Jingjing WU ,  Liang MA ,  Hongjun NI ,  Zhiguo WEN ,  Changpeng LIU ,  Anjali Singhai JAIN ,  Daniel DALY ,  Yadong LI

IPC: H04L12/861 ,  H04L12/875 ,  H04L12/939 ,  H04L12/801 ,  H04L1/18

Abstract: Examples described herein relate to a reliable transport protocol for packet transmission using an Address Family of an eXpress Data Path (AF_XDP) queue framework, wherein the AF_XDP queue framework is to provide a queue for received packet receipt acknowledgements (ACKs). In some examples, an AF_XDP socket is to connect a service with a driver for the network device, one or more queues are associated with the AF_XDP socket, and at least one of the one or more queues comprises a waiting queue for received packet receipt ACKs. In some examples, at least one of the one or more queues is to identify one or more packets for which ACKs have been received. In some examples, the network device is to re-transmit a packet identified by a descriptor in the waiting queue based on non-receipt of an ACK associated with the packet from a receiver.

公开(公告)号：US20230082780A1

公开(公告)日：2023-03-16

申请号：US17471889

申请日：2021-09-10

Applicant: Intel Corporation

Inventor： Chenmin SUN ,  Yipeng WANG ,  Rahul R. SHAH ,  Ren WANG ,  Sameh GOBRIEL ,  Hongjun NI ,  Mrittika GANGULI ,  Edwin VERPLANKE

IPC: G06F9/50

Abstract: Examples described herein include a device interface; a first set of one or more processing units; and a second set of one or more processing units. In some examples, the first set of one or more processing units are to perform heavy flow detection for packets of a flow and the second set of one or more processing units are to perform processing of packets of a heavy flow. In some examples, the first set of one or more processing units and second set of one or more processing units are different. In some examples, the first set of one or more processing units is to allocate pointers to packets associated with the heavy flow to a first set of one or more queues of a load balancer and the load balancer is to allocate the packets associated with the heavy flow to one or more processing units of the second set of one or more processing units based, at least in part on a packet receive rate of the packets associated with the heavy flow.

公开(公告)号：US20210243247A1

公开(公告)日：2021-08-05

申请号：US17238960

申请日：2021-04-23

Applicant: Intel Corporation

Inventor： Shaopeng HE ,  Cunming LIANG ,  Haitao KANG ,  Hongjun NI ,  Jiang YU ,  Ziye YANG ,  Anjali Singhai JAIN ,  Daniel DALY ,  Yadong LI ,  Ping YU ,  Bo CUI ,  Jingjing WU ,  Liang MA ,  Changpeng LIU

IPC: H04L29/08

Abstract: Examples described herein relate to a switch comprising a programmable data plane pipeline, wherein the programmable data plane pipeline is configured to provide microservice-to-microservice communications within a service mesh. In some examples, to provide microservice-to-microservice communications within a service mesh, the programmable data plane pipeline is to perform a forwarding operation for a communication from a first microservice to a second microservice. In some examples, to perform a forwarding operation for a communication from a first microservice to a second microservice, the programmable data plane pipeline is to utilize a reliable transport protocol.

公开(公告)号：US20210208888A1

公开(公告)日：2021-07-08

申请号：US17212560

申请日：2021-03-25

Applicant: Intel Corporation

Inventor： Hao CHANG ,  Xiang WANG ,  Yang HONG ,  Hongjun NI ,  Baoqian LI

IPC: G06F9/30 ,  G06F9/38

Abstract: Methods, software, and apparatus for implementing a high-performance multi-literal matching algorithm. Under aspects of a method, multi-literal matching is used during front-end processing to identify match candidates based on suffix patterns. An extended SHIFT-OR algorithm is performed using the chunk of data as an input to identify match candidates for the suffix patterns, wherein the extended SHIFT-OR algorithm shifts match indicia in the plurality of rows across predetermined bit boundaries and aligns the match indicia corresponding to target suffixes into single columns. Match candidates are indicated when OR'ed column values yield a ‘0’. Match verification for one or more search strings containing the suffix patterns is then performed by a back-end. The scheme eliminates false positives at the predetermined bit boundaries, providing substantial improvement in front-end accuracy and performance.