公开(公告)号：US20200026655A1

公开(公告)日：2020-01-23

申请号：US16586251

申请日：2019-09-27

Applicant: Intel Corporation

Inventor： Zhe WANG ,  Alaa R. Alameldeen ,  Yi Zou ,  Gordon King

IPC: G06F12/0873 ,  G06F12/0811 ,  G06F12/0897 ,  G06F12/02 ,  G06F13/16

Abstract: An apparatus is described. The apparatus includes a memory controller to interface with a multi-level memory, where, an upper level of the multi-level memory is to act as a cache for a lower level of the multi-level memory. The memory controller has circuitry to determine: i) an original address of a slot in the upper level of memory from an address of a memory request in a direct mapped fashion; ii) a miss in the cache for the request because the slot is pinned with data from another address that competes with the address; iii) a partner slot of the slot in the cache in response to the miss; iv) whether there is a hit or miss in the partner slot in the cache for the request.

公开(公告)号：US11526448B2

公开(公告)日：2022-12-13

申请号：US16586251

申请日：2019-09-27

Applicant: Intel Corporation

Inventor： Zhe Wang ,  Alaa R. Alameldeen ,  Yi Zou ,  Gordon King

IPC: G06F12/0811 ,  G06F12/0873 ,  G06F12/02 ,  G06F13/16 ,  G06F12/0897

Abstract: An apparatus is described. The apparatus includes a memory controller to interface with a multi-level memory, where, an upper level of the multi-level memory is to act as a cache for a lower level of the multi-level memory. The memory controller has circuitry to determine: i) an original address of a slot in the upper level of memory from an address of a memory request in a direct mapped fashion; ii) a miss in the cache for the request because the slot is pinned with data from another address that competes with the address; iii) a partner slot of the slot in the cache in response to the miss; iv) whether there is a hit or miss in the partner slot in the cache for the request.