公开(公告)号：US20190310853A1

公开(公告)日：2019-10-10

申请号：US16024808

申请日：2018-06-30

Applicant: Intel Corporation

Inventor： RAHUL BERA ,  ANANT VITHAL NORI ,  SREENIVAS SUBRAMONEY ,  HONG WANG

IPC: G06F9/38 ,  G06F12/0875

Abstract: An apparatus and method for adaptive spatial accelerated prefetching. For example, one embodiment of an apparatus comprises: execution circuitry to execute instructions and process data; a Level 2 (L2) cache to store at least a portion of the data; and a prefetcher to prefetch data from a memory subsystem to the L2 cache in anticipation of the data being needed by the execution unit to execute one or more of the instructions, the prefetcher comprising a buffer to store one or more prefetched memory pages or portions thereof, and signature data indicating detected patterns of access to the one or more prefetched memory pages; wherein the prefetcher is to prefetch one or more cache lines based on the signature data.

公开(公告)号：US20170161096A1

公开(公告)日：2017-06-08

申请号：US15118501

申请日：2014-03-24

Applicant: THIAM WAH LOH ,  GAUTHAM N. CHINYA ,  PER HAMMARLUND ,  REZA FORTAS ,  HONG WANG ,  HUAJIN SUN ,  INTEL CORPORATION

Inventor： THIAM WAH LOH ,  GAUTHAM N. CHINYA ,  PER HAMMARLUND ,  REZA FORTAS ,  HONG WANG ,  HUAJIN SUN

IPC: G06F13/24

CPC classification number: G06F13/24 ,  G06F2213/2404 ,  G06F2213/2406 ,  Y02D10/14

Abstract: A processor is disclosed and includes at least one core including a first core, and interrupt delay logic. The interrupt delay logic is to receive a first interrupt at a first time and delay the first interrupt from being processed by a first time delay that begins at the first time, unless the first interrupt is pending at a second time when a second interrupt is processed by the first core. If the first interrupt is pending at the second time, the interrupt delay logic is to indicate to the first core to begin to process the first interrupt prior to completion of the first time delay. Other embodiments are disclosed and claimed.