公开(公告)号：US09720697B2

公开(公告)日：2017-08-01

申请号：US13608970

申请日：2012-09-10

Applicant: Hong Wang ,  John Shen ,  Ed Grochowski ,  James Paul Held ,  Bryant Bigbee ,  Shivnandan D. Kaushik ,  Gautham Chinya ,  Xiang Zou ,  Per Hammarlund ,  Xinmin Tian ,  Anil Aggarwal ,  Scott Dion Rodgers ,  Prashant Sethi ,  Baiju V. Patel ,  Richard Andrew Hankins

Inventor： Hong Wang ,  John Shen ,  Ed Grochowski ,  James Paul Held ,  Bryant Bigbee ,  Shivnandan D. Kaushik ,  Gautham Chinya ,  Xiang Zou ,  Per Hammarlund ,  Xinmin Tian ,  Anil Aggarwal ,  Scott Dion Rodgers ,  Prashant Sethi ,  Baiju V. Patel ,  Richard Andrew Hankins

IPC: G06F9/46 ,  G06F9/38 ,  G06F9/30 ,  G06F9/48

CPC classification number: G06F9/3867 ,  G06F9/30003 ,  G06F9/30043 ,  G06F9/3005 ,  G06F9/3009 ,  G06F9/30145 ,  G06F9/3017 ,  G06F9/30174 ,  G06F9/3851 ,  G06F9/4843 ,  G06F9/4881

Abstract: In an embodiment, a method is provided. The method includes managing user-level threads on a first instruction sequencer in response to executing user-level instructions on a second instruction sequencer that is under control of an application level program. A first user-level thread is run on the second instruction sequencer and contains one or more user level instructions. A first user level instruction has at least 1) a field that makes reference to one or more instruction sequencers or 2) implicitly references with a pointer to code that specifically addresses one or more instruction sequencers when the code is executed.

公开(公告)号：US20150277949A1

公开(公告)日：2015-10-01

申请号：US14227166

申请日：2014-03-27

Applicant: THIAM WAH LOH ,  GAUTHAM N. CHINYA ,  STEPHEN J. ROBINSON ,  REZA FORTAS ,  HONG WANG ,  HELMUT REINIG ,  PER HAMMARLUND ,  DEEPAK A. MATHAIKUTTY ,  CHRISTIAN ERBEN

Inventor： THIAM WAH LOH ,  GAUTHAM N. CHINYA ,  STEPHEN J. ROBINSON ,  REZA FORTAS ,  HONG WANG ,  HELMUT REINIG ,  PER HAMMARLUND ,  DEEPAK A. MATHAIKUTTY ,  CHRISTIAN ERBEN

IPC: G06F9/455 ,  G06F13/16 ,  G06F13/364 ,  G06F12/14

CPC classification number: G06F9/45558 ,  G06F12/145 ,  G06F13/1684 ,  G06F13/364 ,  G06F2009/45587 ,  G06F2212/1052

Abstract: A processing system includes an interconnect and a processing core, coupled to the interconnect, to execute a plurality of virtual machines each being identified by a respective identifier, and tag, by an identifier of the first virtual machine, a first transaction initiated by a first virtual machine to access the interconnect.

Abstract translation: 处理系统包括耦合到互连的互连和处理核，以执行多个虚拟机，每个虚拟机由相应的标识符标识，并且由第一虚拟机的标识符标记由第一虚拟机发起的第一事务 虚拟机访问互连。

公开(公告)号：US08984199B2

公开(公告)日：2015-03-17

申请号：US10631522

申请日：2003-07-31

Applicant: Per Hammarlund ,  James B. Crossland ,  Shivnandan D. Kaushik ,  Anil Aggarwal

Inventor： Per Hammarlund ,  James B. Crossland ,  Shivnandan D. Kaushik ,  Anil Aggarwal

IPC: G06F13/24 ,  G06F13/32 ,  G06F9/48 ,  G06F9/54

CPC classification number: G06F9/4812 ,  G06F9/544

Abstract: According to an embodiment of the invention, a method and apparatus for inter-processor interrupts in a multi-processor system are described. An embodiment comprises writing an inter-processor interrupt request to a first memory location; monitoring the first memory location; detecting the inter-processor interrupt request in the first memory location; calling a function for the inter-processor interrupt request; and performing the function for the inter-processor interrupt request.

Abstract translation: 根据本发明的实施例，描述了用于多处理器系统中的处理器间中断的方法和装置。 一个实施例包括将处理器间中断请求写入第一存储器位置; 监控第一个内存位置; 检测第一存储器位置中的处理器间中断请求; 调用处理器间中断请求的功能; 并执行处理器间中断请求的功能。

公开(公告)号：US20150032998A1

公开(公告)日：2015-01-29

申请号：US13997243

申请日：2012-02-02

Applicant: Ravi Rajwar ,  Martin G. Dixon ,  Konrad K. Lai ,  Alexandre J. Farcy ,  Bret L. Toll ,  Robert S. Chappell ,  Matthew C. Merten ,  Rajesh S. Parthasarathy ,  Per Hammarlund

Inventor： Ravi Rajwar ,  Martin G. Dixon ,  Konrad K. Lai ,  Alexandre J. Farcy ,  Bret L. Toll ,  Robert S. Chappell ,  Matthew C. Merten ,  Rajesh S. Parthasarathy ,  Per Hammarlund

IPC: G06F9/30

CPC classification number: G06F9/30181 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/30145 ,  G06F9/3834 ,  G06F9/3851 ,  G06F9/3859

Abstract: An apparatus and method is described herein for providing speculation control instructions. An xAcquire and xRelease instruction are provided to define a critical section. In one embodiment, the xAcquire instruction includes a lock instruction with an elision prefix and the xRelease instruction includes a lock release instruction with an elision prefix. As a result, a processor is able to elide locks and transactionally execute a critical section defined in software by xAcquire and xRelease. But by adding only prefix hints, legacy processor are able to execute the same code by just ignoring the hints and executing the critical section traditionally with locks to guarantee mutual exclusion. Moreover, xBegin and xEnd are similarly provided for in an Instruction Set Architecture (ISA) to define a transactional code region. In addition, other control speculation instructions, such as xAbort to enable explicit abort of a critical or transactional code section and xTest to test a state of speculative execution is also provided in the ISA.

Abstract translation: 这里描述了一种用于提供猜测控制指令的装置和方法。 提供xAcquire和xRelease指令来定义关键部分。 在一个实施例中，xAcquire指令包括具有检验前缀的锁定指令，并且xRelease指令包括具有检验前缀的锁定释放指令。 因此，处理器能够通过xAcquire和xRelease来删除锁定和事务性地执行在软件中定义的关键部分。 但是通过仅添加前缀提示，传统处理器能够通过忽略提示并执行传统的锁定关键部分来保证互斥，从而执行相同的代码。 此外，xBegin和xEnd在指令集架构（ISA）中类似地提供以定义事务代码区域。 此外，还在ISA中提供了其他控制推测指令，例如xAbort，以实现关键或事务代码段的显示中止，以及xTest测试推测执行状态。

公开(公告)号：US08607241B2

公开(公告)日：2013-12-10

申请号：US10880638

申请日：2004-06-30

Applicant: Bratin Saha ,  Matthew C. Merten ,  Per Hammarlund

Inventor： Bratin Saha ,  Matthew C. Merten ,  Per Hammarlund

IPC: G06F9/46 ,  G06F9/30 ,  G06F9/40 ,  G06F7/38 ,  G06F9/00 ,  G06F9/44

CPC classification number: G06F9/30021 ,  G06F9/30032 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/3857 ,  G06F9/526 ,  G06F2209/521

Abstract: A method, apparatus, and system are provided for performing compare and exchange operations using a sleep-wakeup mechanism. According to one embodiment, an instruction at a processor is executed to help acquire a lock on behalf of the processor. If the lock is unavailable to be acquired by the processor, the instruction is put to sleep until an event has occurred.

Abstract translation: 提供了一种使用睡眠 - 唤醒机制​​执行比较和交换操作的方法，装置和系统。 根据一个实施例，执行处理器处的指令以帮助代表处理器获取锁定。 如果锁不能由处理器获取，则指令将进入休眠状态，直到发生事件为止。

公开(公告)号：US08464035B2

公开(公告)日：2013-06-11

申请号：US12641534

申请日：2009-12-18

Applicant: Martin G. Dixon ,  Scott D. Rodgers ,  Taraneh Bahrami ,  Stephen H. Gunther ,  Prashant Sethi ,  Per Hammarlund

Inventor： Martin G. Dixon ,  Scott D. Rodgers ,  Taraneh Bahrami ,  Stephen H. Gunther ,  Prashant Sethi ,  Per Hammarlund

IPC: G06F1/32 ,  G06F12/08 ,  G06F9/30

CPC classification number: G06F1/3234 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3228 ,  G06F1/3293 ,  G06F9/30083 ,  G06F9/3009 ,  Y02D10/122 ,  Y02D50/20

Abstract: In one embodiment, the present invention includes a processor having a core with decode logic to decode an instruction prescribing an identification of a location to be monitored and a timer value, and a timer coupled to the decode logic to perform a count with respect to the timer value. The processor may further include a power management unit coupled to the core to determine a type of a low power state based at least in part on the timer value and cause the processor to enter the low power state responsive to the determination. Other embodiments are described and claimed.

公开(公告)号：US08171321B2

公开(公告)日：2012-05-01

申请号：US11964439

申请日：2007-12-26

Applicant: Arvind Kumar ,  Per Hammarlund ,  Glenn Hinton ,  Johan G. Van De Groenendaal

Inventor： Arvind Kumar ,  Per Hammarlund ,  Glenn Hinton ,  Johan G. Van De Groenendaal

IPC: G06F1/00

CPC classification number: G06F1/3287 ,  G06F1/3209 ,  Y02D10/171

Abstract: A low cost, low power consumption scalable architecture is provided to allow a computer system to be managed remotely during all system power states. In a lowest power state, power is only applied to minimum logic necessary to examine a network packet. Power is applied for a short period of time to an execution subsystem and one of a plurality of cores selected to handle processing of received service requests. After processing the received service requests, the computer system returns to the lowest power state.

Abstract translation: 提供了低成本，低功耗的可扩展架构，以允许在所有系统电源状态期间远程管理计算机系统。 在最低功率状态下，功率仅适用于检查网络分组所需的最小逻辑。 将电力短时间施加到执行子系统，并且被选择用于处理所接收的服务请求的处理的多个核心中的一个。 在处理接收到的服务请求之后，计算机系统返回到最低功率状态。

公开(公告)号：US07882339B2

公开(公告)日：2011-02-01

申请号：US11165639

申请日：2005-06-23

Applicant: Quinn A. Jacobson ,  Hong Wang ,  John Shen ,  Gautham N. Chinya ,  Per Hammarlund ,  Xiang Zou ,  Bryant Bigbee ,  Shivnandan D. Kaushik

Inventor： Quinn A. Jacobson ,  Hong Wang ,  John Shen ,  Gautham N. Chinya ,  Per Hammarlund ,  Xiang Zou ,  Bryant Bigbee ,  Shivnandan D. Kaushik

IPC: G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F15/00

CPC classification number: G06F9/526 ,  G06F9/30087 ,  G06F9/30101 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3861

Abstract: A processor may include an address monitor table and an atomic update table to support speculative threading. The processor may also include one or more registers to maintain state associated with execution of speculative threads. The processor may support one or more of the following primitives: an instruction to write to a register of the state, an instruction to trigger the committing of buffered memory updates, an instruction to read the a status register of the state, and/or an instruction to clear one of the state bits associated with trap/exception/interrupt handling. Other embodiments are also described and claimed.

Abstract translation: 处理器可以包括地址监视表和原子更新表以支持推测性线程。 处理器还可以包括一个或多个寄存器以维持与推测线程的执行相关联的状态。 处理器可以支持以下一个或多个原语：写入状态寄存器的指令，触发提交缓冲存储器更新的指令，读取状态状态寄存器的指令和/或 指令清除与陷阱/异常/中断处理相关联的状态位之一。 还描述和要求保护其他实施例。

公开(公告)号：US20100332811A1

公开(公告)日：2010-12-30

申请号：US12879898

申请日：2010-09-10

Applicant: Hong Wang ,  Tor M. Aamodt ,  Pedro Marcuello ,  Jared W. Stark, IV ,  John P. Shen ,  Antonio Gonzalez ,  Per Hammarlund ,  Gerolf F. Hoflehner ,  Perry H. Wang ,  Steve Shih-wei Liao

Inventor： Hong Wang ,  Tor M. Aamodt ,  Pedro Marcuello ,  Jared W. Stark, IV ,  John P. Shen ,  Antonio Gonzalez ,  Per Hammarlund ,  Gerolf F. Hoflehner ,  Perry H. Wang ,  Steve Shih-wei Liao

IPC: G06F9/38

CPC classification number: G06F9/4843 ,  G06F8/433 ,  G06F9/3009 ,  G06F9/3808 ,  G06F9/3832 ,  G06F9/3842 ,  G06F9/3851

Abstract: The latencies associated with retrieving instruction information for a main thread are decreased through the use of a simultaneous helper thread. The helper thread is a speculative prefetch thread to perform instruction prefetch and/or trace pre-build for the main thread.

Abstract translation: 通过使用同时提供的线程来减少与检索主线程的指令信息相关的延迟。 辅助线程是用于为主线程执行指令预取和/或跟踪预构建的推测性预取线程。

公开(公告)号：US07844801B2

公开(公告)日：2010-11-30

申请号：US10632431

申请日：2003-07-31

Applicant: Hong Wang ,  Perry H. Wang ,  Jeffery A. Brown ,  Per Hammarlund ,  George Z. Chrysos ,  Doron Orenstein ,  Steve Shih-wei Liao ,  John P. Shen

Inventor： Hong Wang ,  Perry H. Wang ,  Jeffery A. Brown ,  Per Hammarlund ,  George Z. Chrysos ,  Doron Orenstein ,  Steve Shih-wei Liao ,  John P. Shen

IPC: G06F7/38 ,  G06F9/00 ,  G06F9/44

CPC classification number: G06F9/3842 ,  G06F9/383 ,  G06F9/3851 ,  G06F12/0862

Abstract: Apparatus, system and methods are provided for performing speculative data prefetching in a chip multiprocessor (CMP). Data is prefetched by a helper thread that runs on one core of the CMP while a main program runs concurrently on another core of the CMP. Data prefetched by the helper thread is provided to the helper core. For one embodiment, the data prefetched by the helper thread is pushed to the main core. It may or may not be provided to the helper core as well. A push of prefetched data to the main core may occur during a broadcast of the data to all cores of an affinity group. For at least one other embodiment, the data prefetched by a helper thread is provided, upon request from the main core, to the main core from the helper core's local cache.

Abstract translation: 提供了用于在芯片多处理器（CMP）中执行推测性数据预取的装置，系统和方法。 数据由在CMP的一个核心上运行的辅助线程预取，而主程序在CMP的另一个核心上同时运行。 由辅助线程预取的数据被提供给辅助核心。 对于一个实施例，由辅助线程预取的数据被推送到主核心。 它也可以也可以不被提供给辅助核心。 在将数据广播到亲和组的所有核心的过程中，可能会将预取数据推送到主核心。 对于至少另一个实施例，根据主核心的请求，从辅助核心的本地高速缓存提供由辅助线程预取的数据到主核心。