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    DEVICE, METHOD AND SYSTEM FOR SELECTIVELY DISABLING A POWER CLAMP CIRCUIT
    2.
    发明申请
    DEVICE, METHOD AND SYSTEM FOR SELECTIVELY DISABLING A POWER CLAMP CIRCUIT 有权

    公开(公告)号：US20240421150A1

    公开(公告)日：2024-12-19

    申请号：US18209358

    申请日：2023-06-13

    Applicant: Intel Corporation

    Inventor： Ritesh Agarwal ,  Harshit Dhakad ,  Krzysztof Domanski

    IPC: H01L27/02

    Abstract: Techniques and mechanisms for selectively disabling functionality of a power clamp circuit which is to mitigate damage due to electrostatic discharge (ESD). In an embodiment, a shut-off circuit is coupled to receive a control signal which indicates an actual or expected future power state transition of a load. The power clamp circuit comprises a pull-up circuit and a pull-down circuit which are coupled in series between a first interconnect and a second interconnect, which are to receive a first supply voltage and a second supply voltage, respectively. Based on a filtered version of the control signal, the shut-off circuit generates a first one or more signals to selectively disable the pull-up circuit. The shut-off circuit further generates a second one or more signals, based on the filtered version of the control signal, to selectively disable the pull-down circuit.

    HIGH-FREQUENCY INTERFACE CIRCUIT PROTECTION FROM ELECTROSTATIC DISCHARGE EVENTS
    3.
    发明申请
    HIGH-FREQUENCY INTERFACE CIRCUIT PROTECTION FROM ELECTROSTATIC DISCHARGE EVENTS 有权

    公开(公告)号：US20250007278A1

    公开(公告)日：2025-01-02

    申请号：US18216447

    申请日：2023-06-29

    Applicant: Intel Corporation

    Inventor： Krzysztof Domanski ,  Robert Haeussler ,  Harshit Dhakad

    IPC: H02H9/02

    Abstract: An integrated circuit (IC) device comprises a conductive contact at a surface of the IC device. First and second circuitry are coupled with the conductive contact. First and second supply lines are coupled with and provide power to the first circuitry, the first supply line providing a first voltage, and the second supply line providing a second voltage. The second circuitry is further coupled with the second supply line and a third supply line. The third supply line is to provide a third voltage and may provide a path for a current associated with an electrostatic discharge (ESD) event. A resistive element is coupled between the first supply line and the third supply line. The resistive element may reduce a current in the first supply line associated with an ESD event.

    SERIAL INTERFACE PROVIDING ELECTROSTATIC DISCHARGE PROTECTION
    5.
    发明申请
    SERIAL INTERFACE PROVIDING ELECTROSTATIC DISCHARGE PROTECTION 有权

    公开(公告)号：US20250006726A1

    公开(公告)日：2025-01-02

    申请号：US18216442

    申请日：2023-06-29

    Applicant: Intel Corporation

    Inventor： Krzysztof Domanski ,  Harshit Dhakad

    IPC: H01L27/02 ,  H01L27/06

    Abstract: An integrated circuit (IC) device comprises a conductive contact at a surface of the IC device. A resistive element is coupled between the conductive contact and first circuitry. Second circuitry is coupled between the resistive element and the conductive contact. The second circuitry is further coupled with a supply line and comprises at least one of a diode or a power clamp. The resistive element is disposed in a first metallization layer of the IC device. A first dielectric layer is adjacent to the first metallization layer. A second metallization layer is adjacent to the first dielectric layer. A height of the first dielectric layer and the second metallization layer is a first distance. A zone overlaps the resistive element, and extends a second distance away from the resistive element. The zone is free of conductive material and the second distance is greater than the first distance.

    DEVICE, METHOD AND SYSTEM FOR IMPROVED ELECTROSTATIC DISCHARGE PROTECTION
    6.
    发明申请
    DEVICE, METHOD AND SYSTEM FOR IMPROVED ELECTROSTATIC DISCHARGE PROTECTION 有权

    公开(公告)号：US20240421591A1

    公开(公告)日：2024-12-19

    申请号：US18209361

    申请日：2023-06-13

    Applicant: Intel Corporation

    Inventor： Harshit Dhakad ,  Yossi Shoshany ,  Sergey Sofer ,  Suhwan Kim ,  Krzysztof Domanski

    IPC: H02H9/04 ,  H01L27/02 ,  H03K19/003

    Abstract: Techniques and mechanisms for a DC-DC voltage converter to mitigate a risk of damage to circuitry due to electrostatic discharge (ESD). In an embodiment, a protection circuit of the DC-DC voltage converter comprises a pull-up circuit and a pull-down circuit which are coupled in series between a first interconnect and a second interconnect, which are to receive a first supply voltage and a second supply voltage, respectively. A voltage divider comprises capacitors which are coupled in series with each other between the first interconnect and the second interconnect. Control circuitry is coupled with the voltage divider, and is further coupled to automatically configure a first operational mode based on an ESD event. During the first mode, the pull-up circuit is disabled and the pull-down circuit is enabled. In another embodiment, a resistor-capacitor (RC) circuit automatically transitions the protection circuit from the first mode.

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