公开(公告)号：US20210026769A1

公开(公告)日：2021-01-28

申请号：US17042037

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Malini K. BHANDARU ,  Iosif GASPARAKIS ,  Sunku RANGANATH ,  Liyong QIAO ,  Rui ZANG ,  Dakshina ILANGOVAN ,  Shaohe FENG ,  Edwin VERPLANKE ,  Priya AUTEE ,  Lin A. YANG

IPC: G06F12/0806 ,  G06F9/54 ,  G06F9/50

Abstract: Examples include techniques to support a holistic view of cache class of service (CLOS). Examples include allocating processor cache resources to a plurality of CLOS. The allocation of processor cache resources to include allocation of cache ways for an n-way set of associative cache. Examples include monitoring usage of the plurality of CLOS to determine processor cache resource usage and to report the processor cache resource usage.

公开(公告)号：US20240195707A1

公开(公告)日：2024-06-13

申请号：US18394888

申请日：2023-12-22

Applicant: Intel Corporation

Inventor： Iosif GASPARAKIS ,  Malini K. BHANDARU ,  Ranganath SUNKU

IPC: H04L41/5003 ,  G06F9/455 ,  G06F12/084 ,  G06F12/0864 ,  H04L43/08 ,  H04L47/70 ,  H04L67/568

CPC classification number: H04L41/5003 ,  G06F9/45558 ,  G06F12/084 ,  G06F12/0864 ,  H04L43/08 ,  H04L47/82 ,  H04L67/568 ,  G06F2009/4557 ,  G06F2009/45583 ,  G06F2009/45595 ,  G06F2212/1024 ,  G06F2212/154 ,  G06F2212/6032

Abstract: Technologies for managing cache quality of service (QoS) include a compute node that includes a network interface controller (NIC) configured to identify a total amount of available shared cache ways of a last level cache (LLC) of the compute node and identify a destination address for each of a plurality of virtual machines (VMs) managed by the compute node. The NIC is further configured to calculate a recommended amount of cache ways for each workload type associated with VMs based on network traffic to be received by the NIC and processed by each of the VMs, wherein the recommended amount of cache ways includes a recommended amount of hardware I/O LLC cache ways and a recommended amount of isolated LLC cache ways usable to update a cache QoS register that includes the recommended amount of cache ways for each workload type. Other embodiments are described herein.