公开(公告)号：US09588801B2

公开(公告)日：2017-03-07

申请号：US14024451

申请日：2013-09-11

Applicant: Intel Corporation

Inventor： Irina Calciu ,  Justin E Gottschlich ,  Tatiana Shpeisman ,  Gilles A Pokam

IPC: G06F9/30 ,  G06F9/46 ,  G06F12/14 ,  G06F9/52

CPC classification number: G06F9/467 ,  G06F9/30181 ,  G06F9/526 ,  G06F12/1466

Abstract: An apparatus and method for improving the efficiency with which speculative critical sections are executed within a transactional memory architecture. For example, a method in accordance with one embodiment comprises: waiting to execute a speculative critical section of program code until a lock is freed by a current transaction; responsively executing the speculative critical section to completion upon detecting that the lock has been freed, regardless of whether the lock is held by another transaction during the execution of the speculative critical section; once execution of the speculative critical section is complete, determining whether the lock is taken; and if the lock is not taken, then committing the speculative critical section and, if the lock is taken, then aborting the speculative critical section.

Abstract translation: 一种用于提高在事务存储架构内执行投机关键部分的效率的装置和方法。 例如，根据一个实施例的方法包括：等待执行程序代码的推测性临界部分，直到当前事务释放锁定为止; 在检测到锁已经被释放时响应地执行推测性关键部分以完成，而不管在推测性关键部分的执行期间锁是否被另一事务持有; 一旦投机关键部分的执行完成，确定是否采取锁定; 如果不采取锁定，则提交投机性关键部分，如果采取锁定，则中止推测性关键部分。

公开(公告)号：US20160371036A1

公开(公告)日：2016-12-22

申请号：US15160786

申请日：2016-05-20

Applicant: Intel Corporation

Inventor： Irina Calciu ,  Justin E. Gottschlich ,  Tatiana Shpeisman

IPC: G06F3/06 ,  G06F9/46

CPC classification number: G06F3/0659 ,  G06F3/0613 ,  G06F3/067 ,  G06F3/0673 ,  G06F9/44 ,  G06F9/466 ,  G06F9/467 ,  G06F12/0813

Abstract: Techniques for improved transactional memory management are described. In one embodiment, for example, an apparatus may comprise a processor element, an execution component for execution by the processor element to concurrently execute a software transaction and a hardware transaction according to a transactional memory process, a tracking component for execution by the processor element to activate a global lock to indicate that the software transaction is undergoing execution, and a finalization component for execution by the processor element to commit the software transaction and deactivate the global lock when execution of the software transaction completes, the finalization component to abort the hardware transaction when the global lock is active when execution of the hardware transaction completes. Other embodiments are described and claimed.

公开(公告)号：US09361152B2

公开(公告)日：2016-06-07

申请号：US14129936

申请日：2013-07-15

Applicant: Intel Corporation

Inventor： Irina Calciu ,  Justin E. Gottschlich ,  Tatiana Shpeisman

IPC: G06F12/10 ,  G06F9/46 ,  G06F9/44 ,  G06F12/08 ,  G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0613 ,  G06F3/067 ,  G06F3/0673 ,  G06F9/44 ,  G06F9/466 ,  G06F9/467 ,  G06F12/0813

Abstract: Techniques for improved transactional memory management are described. In one embodiment, for example, an apparatus may comprise a processor element, an execution component for execution by the processor element to concurrently execute a software transaction and a hardware transaction according to a transactional memory process, a tracking component for execution by the processor element to activate a global lock to indicate that the software transaction is undergoing execution, and a finalization component for execution by the processor element to commit the software transaction and deactivate the global lock when execution of the software transaction completes, the finalization component to abort the hardware transaction when the global lock is active when execution of the hardware transaction completes. Other embodiments are described and claimed.

Abstract translation: 描述了改进的事务性内存管理技术。 在一个实施例中，例如，设备可以包括处理器元件，用于由处理器元件执行以根据事务存储器进程同时执行软件事务和硬件事务的执行部件，用于由处理器元件执行的跟踪部件 激活全局锁以指示软件事务正在执行;以及最终化组件，用于由处理器元件执行以提交软件事务，并且在执行软件事务完成时停用全局锁定，终止组件中止硬件 当执行硬件事务完成时，全局锁活动时的事务。 描述和要求保护其他实施例。

公开(公告)号：US10001949B2

公开(公告)日：2018-06-19

申请号：US15160786

申请日：2016-05-20

Applicant: Intel Corporation

Inventor： Irina Calciu ,  Justin E. Gottschlich ,  Tatiana Shpeisman

IPC: G06F12/00 ,  G06F3/06 ,  G06F9/44 ,  G06F12/0813 ,  G06F9/46

CPC classification number: G06F3/0659 ,  G06F3/0613 ,  G06F3/067 ,  G06F3/0673 ,  G06F9/44 ,  G06F9/466 ,  G06F9/467 ,  G06F12/0813

Abstract: Techniques for improved transactional memory management are described. In one embodiment, for example, an apparatus may comprise a processor element, an execution component for execution by the processor element to concurrently execute a software transaction and a hardware transaction according to a transactional memory process, a tracking component for execution by the processor element to activate a global lock to indicate that the software transaction is undergoing execution, and a finalization component for execution by the processor element to commit the software transaction and deactivate the global lock when execution of the software transaction completes, the finalization component to abort the hardware transaction when the global lock is active when execution of the hardware transaction completes. Other embodiments are described and claimed.

公开(公告)号：US09971627B2

公开(公告)日：2018-05-15

申请号：US14225804

申请日：2014-03-26

Applicant: Intel Corporation

Inventor： Irina Calciu ,  Justin E. Gottschlich ,  Tatiana Shpeisman ,  Gilles A. Pokam

IPC: G06F9/52 ,  G06F9/46

CPC classification number: G06F9/467 ,  G06F9/528

Abstract: In an embodiment of a transactional memory system, an apparatus includes a processor and an execution logic to enable concurrent execution of at least one first software transaction of a first software transaction mode and a second software transaction of a second software transaction mode and at least one hardware transaction of a first hardware transaction mode and at least one second hardware transaction of a second hardware transaction mode. In one example, the execution logic may be implemented within the processor. Other embodiments are described and claimed.

公开(公告)号：US09697040B2

公开(公告)日：2017-07-04

申请号：US14226312

申请日：2014-03-26

Applicant: Intel Corporation

Inventor： Justin E. Gottschlich ,  Gilles A. Pokam ,  Shiliang Hu ,  Rolf Kassa ,  Youfeng Wu ,  Irina Calciu

IPC: G06F9/44 ,  G06F9/45 ,  G06F9/46 ,  G06F11/34 ,  G06F11/36

CPC classification number: G06F9/467 ,  G06F11/34 ,  G06F11/362 ,  G06F11/3648

Abstract: A system is disclosed that includes a processor and a dynamic random access memory (DRAM). The processor includes a hybrid transactional memory (HyTM) that includes hardware transactional memory (HTM), and a program debugger to replay a program that includes an HTM instruction and that has been executed has been executed using the HyTM. The program debugger includes a software emulator that is to replay the HTM instruction by emulation of the HTM. Other embodiments are disclosed and claimed.