公开(公告)号：US20170177500A1

公开(公告)日：2017-06-22

申请号：US14979038

申请日：2015-12-22

Applicant: Intel Corporation

Inventor： VEDVYAS SHANBHOGUE ,  CHRISTOPHER BRYANT ,  JEFF WIEDEMEIER

IPC: G06F12/10 ,  G06F12/08

CPC classification number: G06F12/1045 ,  G06F12/0875 ,  G06F12/1027 ,  G06F12/1475 ,  G06F2212/1024 ,  G06F2212/452 ,  G06F2212/684

Abstract: An apparatus and method for sub-page extended page table protection. For example, one embodiment of an apparatus comprises: a page miss handler to perform a page walk using a guest physical address (GPA) and to detect whether a page identified with the GPA is mapped with sub-page permissions; a sub-page control storage to store at least one GPA and other data related to a sub-page; the page miss handler to determine whether the GPA is programmed in the sub-page control storage; and the page miss handler to send a translation to a translation lookaside buffer (TLB) with a sub-page protection indication set to cause a matching of the sub-page control storage when an access matches a TLB entry with sub-page protection indication.