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公开(公告)号：US20250113430A1
公开(公告)日：2025-04-03
申请号：US18513045
申请日：2023-11-17
Applicant: Intel Corporation
Inventor： Venkata Mahesh Gunnam , Rakesh Yedri , Phani Alaparthi , David Elayaraj Samaraj , Jackson C.P. Kong , Bala Subramanya , Navneet Kumar Singh , Yagnesh V. Waghela
Abstract: Technologies for reducing the impact of inductors on electrical traces are disclosed. In an illustrative embodiment, conductive ink is applied in a silk screen layer on top of a solder mask of a circuit board. The conductive ink forms shield regions under and near where inductors are placed and/or where a power plane is routed. The conductive shield regions may be coupled to a ground plane in the circuit board. The conductive shield regions can partially shield traces under and near the inductor, reducing the noise induced on nearby traces. The conductive shield regions can allow traces for high-speed input/output signals to be routed closer to the inductor, reducing the size, number of layers, and/or cost of the circuit board. In some embodiments, the conductive shield regions can shield emissions from the power plane, reducing interference on antennas of a device.
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公开(公告)号：US20220015246A1
公开(公告)日：2022-01-13
申请号：US17482356
申请日：2021-09-22
Applicant: Intel Corporation
Inventor： Ranjul Balakrishnan , Sandesh G. Krishnamurthy , Jackson C.P. Kong
Abstract: Technologies for shielding an inductor on a circuit board are disclosed. In the illustrative embodiments, a circuit board has a voltage regulator on top of it and one or more signal traces routed beneath or near the voltage regulator. Partial metal vias are positioned between the signal traces and the voltage regulator. The partial metal vias extend from one trace layer of a circuit board towards another trace layer, but the partial metal vias do not connect the two trace layers. The partial metal vias partially shield the signal traces from noise caused by the voltage regulator.
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