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公开(公告)号:US20240329873A1
公开(公告)日:2024-10-03
申请号:US18736227
申请日:2024-06-06
Applicant: Intel Corporation
Inventor: Ho-Ming LEUNG , Salma Mirza JOHNSON , Jackson ELLIS , Daniel Christian BIEDERMAN
IPC: G06F3/06
CPC classification number: G06F3/0656 , G06F3/0604 , G06F3/0679
Abstract: Examples described herein relate to a device that includes: a host interface; and circuitry to: based on allocation of a region in a buffer, wherein the buffer is associated with Non-volatile Memory Express over Fabrics (NVMe-oF) transactions: based on a first size of compressed data to be stored in the buffer, deallocate a portion of the region in the buffer and store the compressed data of the first size into a second portion of the region in the buffer and based on a second size of the compressed data to be stored in the buffer, utilize the allocated region in the buffer to store the compressed data of the second size.
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公开(公告)号:US20200089537A1
公开(公告)日:2020-03-19
申请号:US16689895
申请日:2019-11-20
Applicant: Intel Corporation
Inventor: Shirish BAHIRAT , David B. CARLTON , Jackson ELLIS , Jonathan M. HUGHES , David J. PELSTER , Neelesh VEMULA
Abstract: A solid-state drive that can service multiple users or tenants and workloads (that is, multiple tenants) by enabling assigned bandwidth share of the solid-state drive across tenants is provided. The assigned bandwidth share is enabled for command submissions within a same assigned domain in addition to a weighted bandwidth share and quality of service control across different domains from all tenants.
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公开(公告)号:US20240211392A1
公开(公告)日:2024-06-27
申请号:US18434569
申请日:2024-02-06
Applicant: Intel Corporation
Inventor: Salma Mirza JOHNSON , Jose NIELL , Bradley A. BURRES , Jackson ELLIS , Yadong LI , Jayaram BHAT , Tony HURSON
IPC: G06F12/02
CPC classification number: G06F12/0246
Abstract: Examples described herein relate to circuitry to allocate an Non-volatile Memory Express (NVMe) bounce buffer in virtual memory that is associated with an NVMe command and perform an address translation to an NVMe bounce buffer based on receipt of a response to the NVMe command from an NVMe target. In some examples, the circuitry is to translate the virtual address to a physical address for the NVMe bounce buffer based on receipt of a response to the NVMe command from an NVMe target.
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公开(公告)号:US20200264800A1
公开(公告)日:2020-08-20
申请号:US16865566
申请日:2020-05-04
Applicant: Intel Corporation
Inventor: Piotr WYSOCKI , Sanjeev N. TRIKA , Gregory B. TUCKER , Jackson ELLIS , Jonathan M. HUGHES
Abstract: An embodiment of an electronic storage system includes one or more storage drives, at least one or more of the storage drives supporting erasure coding (EC); and a controller including logic to control local access to the one or more storage drives. The controller, in response to a write command, is to for one or more storage drives, allocate an intermediate buffer in the storage drive's non-volatile memory (NVM) to store intermediate data. The controller is to issue commands to a first storage drive to read old data, compute the intermediate data of the first storage drive as XOR of the old data and new data received in the write command, and atomically write the intermediate data of the first storage drive to the intermediate buffer of the first storage drive and write the new data to the first storage drive's NVM. The controller is to read the intermediate data of the first storage drive from the intermediate buffer of the first storage drive. The controller is further to issue commands to one or more EC storage drives to read the old data, compute result data as the old data XOR a galois field coefficient of the one or more EC storage drives multiplied by the intermediate data, and atomically write the old data to the intermediate buffer of the one or more EC storage drives and write the result data to the one or more EC storage drive's NVM. Other embodiments are disclosed and claimed.
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