公开(公告)号：US20220083280A1

公开(公告)日：2022-03-17

申请号：US17536956

申请日：2021-11-29

Applicant: Intel Corporation

Inventor： Holman SU ,  Mark Anthony GOLEZ ,  Sarvesh Varakabe GANGADHAR ,  David J. PELSTER

IPC: G06F3/06 ,  G06F12/10

Abstract: Read Quality of Service (rQoS) in the solid state drive is improved by reducing latency for host random read workloads. Host read operations for random read workloads are prioritized in the solid state drive over program operations for garbage collection to reduce latency for random read workloads. The program time (tProg) and other associated latencies such as program-suspend-resume overhead, and firmware process overhead to dispatch the program are minimized by minimizing the number of program commands used for garbage collection while the solid state drive is performing read operations for a random read workload for a host read operation, allowing the solid state drive to prioritize host read operations for random read workloads while ensuring that there is no impact to the amount of written data that is on the solid state drive.

公开(公告)号：US20190043556A1

公开(公告)日：2019-02-07

申请号：US16147446

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Mark Anthony GOLEZ ,  David J. PELSTER ,  Xin GUO ,  Paul D. RUBY

IPC: G11C11/406 ,  G11C8/12

CPC classification number: G11C11/40611 ,  G11C8/12 ,  G11C11/40603 ,  G11C11/40618 ,  G11C13/0023 ,  G11C13/0033 ,  G11C13/0061 ,  G11C16/08 ,  G11C16/32 ,  G11C16/3418 ,  G11C16/349 ,  G11C2211/4063

Abstract: A refreshing method is described. The method includes recognizing a set of blocks of a non-volatile memory for refreshing and then refreshing a subset of the data within the blocks, where, invalid data within the blocks is not recognized for refreshing and a group of blocks whose oldest data has not aged for a pre-set time period is not recognized for refreshing.

公开(公告)号：US20190243577A1

公开(公告)日：2019-08-08

申请号：US16388761

申请日：2019-04-18

Applicant: INTEL CORPORATION

Inventor： David J. PELSTER ,  David B. CARLTON ,  Mark Anthony GOLEZ ,  Xin GUO ,  Aliasgar S. MADRASWALA ,  Sagar S. SIDHPURA ,  Sagar UPADHYAY ,  Neelesh VEMULA ,  Yogesh B. WAKCHAURE ,  Ye ZHANG

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679

Abstract: A data structure is maintained for performing a program operation that is allowed to be suspended to perform reads in a NAND device, where the data structure indicates a plurality of tiers, where each tier of the plurality of tiers has a number of allowed suspends of the program operation while executing in the tier, and where a sum of the number of allowed suspends for all tiers of the plurality of tiers equals a maximum allowed number of suspends of the program operation. In response to performing a resume of the program operation, after performing a read following a suspend of the program operation, a determination is made of a tier of the plurality of tiers for the program operation and a subsequent suspend of the program operation is performed only after a measure of progress of the program operation has been exceeded in the determined tier.

公开(公告)号：US20200089537A1

公开(公告)日：2020-03-19

申请号：US16689895

申请日：2019-11-20

Applicant: Intel Corporation

Inventor： Shirish BAHIRAT ,  David B. CARLTON ,  Jackson ELLIS ,  Jonathan M. HUGHES ,  David J. PELSTER ,  Neelesh VEMULA

IPC: G06F9/50 ,  G06F9/52 ,  G06F9/46 ,  G06F9/54 ,  G06F9/48 ,  G06F3/06

Abstract: A solid-state drive that can service multiple users or tenants and workloads (that is, multiple tenants) by enabling assigned bandwidth share of the solid-state drive across tenants is provided. The assigned bandwidth share is enabled for command submissions within a same assigned domain in addition to a weighted bandwidth share and quality of service control across different domains from all tenants.

公开(公告)号：US20160379715A1

公开(公告)日：2016-12-29

申请号：US14752817

申请日：2015-06-26

Applicant: INTEL CORPORATION

Inventor： David J. PELSTER ,  Yogesh B. WAKCHAURE ,  Xin GUO ,  Paul D. RUBY ,  Justin R. DAYACAP ,  Joseph F. DOLLER ,  Robert E. FRICKEY

IPC: G11C16/16 ,  G11C16/34 ,  G11C16/26

CPC classification number: G11C16/16 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C16/32 ,  G11C16/3445 ,  G11C2216/20

Abstract: Provided are an apparatus, memory controller and method for performing a block erase operation with respect to a non-volatile memory. A command is generated to perform a portion of the block erase operation. At least one read or write operation is performed after executing the command. An additional instance of the command is executed in response to determining that the block erase operation did not complete after performing the at least one read or write operation.

Abstract translation: 提供了一种用于对非易失性存储器执行块擦除操作的装置，存储器控制器和方法。 产生用于执行块擦除操作的一部分的命令。 在执行命令后至少执行一次读或写操作。 响应于在执行至少一个读或写操作之后确定块擦除操作未完成，执行命令的附加实例。

公开(公告)号：US20190227749A1

公开(公告)日：2019-07-25

申请号：US16367638

申请日：2019-03-28

Applicant: Intel Corporation

Inventor： Yogesh B. WAKCHAURE ,  Aliasgar S. MADRASWALA ,  David J. PELSTER ,  Donia SEBASTIAN ,  Curtis GITTENS ,  Xin GUO ,  Neelesh VEMULA ,  Varsha REGULAPATI ,  Naga Kiranmayee UPADHYAYULA

IPC: G06F3/06 ,  G11C16/04 ,  G11C16/26

Abstract: Independent multi-plane commands for non-volatile memory devices are described. In one example, a three-dimensional (3D) NAND memory device includes 3D NAND dies, each die including multiple planes of memory cells. The device includes input/output (I/O) circuitry to receive multiple commands from a host, each of the received commands to access one of the planes. The device includes logic (which can be implemented with, for example, an ASIC controller, firmware, or both) to queue the commands in separate queues for each of the planes based on a target plane of each of the commands. The logic issues the commands to their target planes independent of other planes' status, and tracks completion status of the commands independently for each plane.

公开(公告)号：US20190043593A1

公开(公告)日：2019-02-07

申请号：US15959538

申请日：2018-04-23

Applicant: Intel Corporation

Inventor： Xin GUO ,  Yu DU ,  Curtis GITTENS ,  David J. PELSTER ,  Donia SEBASTIAN

IPC: G11C16/30 ,  G11C16/26 ,  G11C16/32

Abstract: A reduction in Quality of Service (QoS) latency for host read commands in a power limited operation mode in a storage device is provided. A priority level is assigned to a host command using weighted round robin arbitration. Power resources are allocated based on the priority levels assigned to host commands to minimize host read command latency in the power limited operation mode.

公开(公告)号：US20190227884A1

公开(公告)日：2019-07-25

申请号：US16370644

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Peng LI ,  David J. PELSTER ,  Gamil CAIN ,  Ryan J. NORTON

IPC: G06F11/14 ,  G06F3/06 ,  G06F12/14 ,  G06F11/30

Abstract: A solid state drive (SSD) includes a nonvolatile memory array and a cache memory. The nonvolatile memory array has an encrypted integrated memory buffer (IMB) space. The cache memory has a decrypted copy of the IMB and an encrypted backup copy of the IMB. In power loss recovery (PLR) after a power loss imminent (PLI) event, the SSD can determine whether to recover the unencrypted copy of the IMB or the backup encrypted copy. The backup encrypted copy can reduce the risk of loss of data in the IMB in the event that multiple PLI events occur and a corrupted copy of the IMB is used to overwrite the IMB in the nonvolatile memory during a previous PLR.

公开(公告)号：US20170046073A1

公开(公告)日：2017-02-16

申请号：US14822793

申请日：2015-08-10

Applicant: INTEL CORPORATION

Inventor： Xin GUO ,  Feng ZHU ,  Eric L. HOFFMAN ,  Jing-Jing LI ,  David J. PELSTER

IPC: G06F3/06 ,  G11C5/02 ,  G06F12/10

CPC classification number: G06F3/0608 ,  G06F3/064 ,  G06F3/0679 ,  G06F12/10 ,  G06F2212/1044 ,  G06F2212/152 ,  G06F2212/202 ,  G06F2212/253 ,  G06F2212/657 ,  G11C29/76

Abstract: Provided are a method and apparatus for remapping logical to physical addresses for a non-volatile memory having dies. Bands extend through the dies and planes in the dies extending through the bands define addressable blocks. A first remapping of a logical-to-physical mapping is performed by remapping logical addresses of blocks in a first end of the bands that map to defective physical blocks to map to good physical blocks at a second end of the bands. After performing the first remapping, a second remapping of the logical-to-physical mapping is performed by remapping logical addresses in the second end of bands that map to defective blocks to map to good physical blocks in the first end of bands.

Abstract translation: 提供了一种用于对具有管芯的非易失性存储器重新映射逻辑到物理地址的方法和装置。 带延伸穿过模具，延伸穿过带的模具中的平面定义可寻址块。 通过重新映射映射到不良物理块的频带的第一端中的块的逻辑地址，以在频带的第二端映射到良好的物理块来执行逻辑到物理映射的第一重映射。 在执行第一重映射之后，通过重新映射映射到缺陷块的频带的第二端中的逻辑地址来进行逻辑到物理映射的第二重映射，以映射到频带的第一端中的良好的物理块。