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    MEDIA STREAMING ENDPOINT
    1.
    发明申请
    MEDIA STREAMING ENDPOINT 有权

    公开(公告)号：US20220224746A1

    公开(公告)日：2022-07-14

    申请号：US17712059

    申请日：2022-04-01

    申请人： Intel Corporation

    发明人： Yadong LI ,  Changliang L. WANG ,  Bradley A. BURRES

    IPC分类号： H04L65/70 ,  H04L65/65 ,  H04L43/0823

    摘要： Examples described herein relate to a network interface device that includes circuitry to: receive a request to perform offloaded media encoding and packetization prior to transmission of the media to a receiver, wherein the media comprises video and audio; perform encoding of the media; perform packetization of the encoded media into one or more packets based on Real-time Transport Protocol (RTP) protocol; and cause transmission of the one or more packets to the receiver.

    BUFFER ALLOCATION
    3.
    发明公开
    BUFFER ALLOCATION 审中-公开

    公开(公告)号：US20240211392A1

    公开(公告)日：2024-06-27

    申请号：US18434569

    申请日：2024-02-06

    申请人： Intel Corporation

    发明人： Salma Mirza JOHNSON ,  Jose NIELL ,  Bradley A. BURRES ,  Jackson ELLIS ,  Yadong LI ,  Jayaram BHAT ,  Tony HURSON

    IPC分类号： G06F12/02

    CPC分类号： G06F12/0246

    摘要： Examples described herein relate to circuitry to allocate an Non-volatile Memory Express (NVMe) bounce buffer in virtual memory that is associated with an NVMe command and perform an address translation to an NVMe bounce buffer based on receipt of a response to the NVMe command from an NVMe target. In some examples, the circuitry is to translate the virtual address to a physical address for the NVMe bounce buffer based on receipt of a response to the NVMe command from an NVMe target.

    DYNAMIC CONFIGURATION OF INPUT/OUTPUT CONTROLLER ACCESS LANES
    4.
    发明申请
    DYNAMIC CONFIGURATION OF INPUT/OUTPUT CONTROLLER ACCESS LANES 有权

    公开(公告)号：US20210326285A1

    公开(公告)日：2021-10-21

    申请号：US17207135

    申请日：2021-03-19

    申请人： Intel Corporation

    发明人： Balaji PARTHASARATHY ,  Ramamurthy KRITHIVAS ,  Bradley A. BURRES ,  Pawel SZYMANSKI ,  Yi-Feng LIU

    IPC分类号： G06F13/40 ,  G06F9/4401 ,  G06F9/445

    摘要： Generally, this disclosure provides systems, devices, methods and computer readable media for dynamic configuration and enforcement of access lanes to I/O controllers. The System may include a plurality of Input/Output (I/O) controllers and a plurality of lanes. The system may also include a lane mapping module configured to multiplex at least one of the I/O controllers to at least one of the lanes based on a configuration. The system may further include a first processor configured to detect a change request, the change request to modify the configuration from an existing configuration to a new configuration; and a second processor configured to: verify that the new configuration is valid based on a stock keeping unit (SKU) associated with the system; and, if the verification is successful, store the new configuration in non-volatile memory and reset the system.

    PROGRAMMABLE ARCHITECTURE FOR STATEFUL DATA PLANE EVENT PROCESSING
    6.
    发明申请
    PROGRAMMABLE ARCHITECTURE FOR STATEFUL DATA PLANE EVENT PROCESSING 有权

    公开(公告)号：US20230139762A1

    公开(公告)日：2023-05-04

    申请号：US18089453

    申请日：2022-12-27

    申请人： Intel Corporation

    发明人： Stephen IBANEZ ,  Robert SOUTHWORTH ,  Salma Mirza JOHNSON ,  Vered BAR BRACHA ,  Bradley A. BURRES

    IPC分类号： G06F9/50 ,  G06F9/54 ,  G06F9/52

    摘要： Examples described herein relate to a network interface device that includes a programmable event processing architecture comprising a plurality of programmable event processors. When the plurality of programmable event processors are operational, one or more of the programmable event processors are to perform memory accesses separate from compute operations, group one or more events into at least one group, enforce atomic processing of other events within a group of the at least one group, wherein the atomic processing comprises propagation of state changes to among events of the group, and perform parallel processing of events belonging to different groups.

    PROGRAMMABLE TRANSPORT PROTOCOL ARCHITECTURE
    8.
    发明申请
    PROGRAMMABLE TRANSPORT PROTOCOL ARCHITECTURE 有权

    公开(公告)号：US20230127722A1

    公开(公告)日：2023-04-27

    申请号：US18089486

    申请日：2022-12-27

    申请人： Intel Corporation

    发明人： Stephen IBANEZ ,  Robert SOUTHWORTH ,  Salma Mirza JOHNSON ,  Vered BAR BRACHA ,  Bradley A. BURRES

    IPC分类号： G06F9/54 ,  G06F9/48

    摘要： Examples described herein relate to a network interface device that includes a programmable event processing architecture that includes a plurality of programmable event processors. In some examples, the plurality of programmable event processors are to perform memory accesses separate from compute operations. In some examples, the plurality of programmable event processors are to group one or more events into at least one group. In some examples, the plurality of programmable event processors are to perform parallel processing of events belonging to different groups. In some examples, the plurality of programmable event processors are programmed to perform at least one transport protocol.