公开(公告)号：US20240211392A1

公开(公告)日：2024-06-27

申请号：US18434569

申请日：2024-02-06

Applicant: Intel Corporation

Inventor： Salma Mirza JOHNSON ,  Jose NIELL ,  Bradley A. BURRES ,  Jackson ELLIS ,  Yadong LI ,  Jayaram BHAT ,  Tony HURSON

IPC: G06F12/02

CPC classification number: G06F12/0246

Abstract: Examples described herein relate to circuitry to allocate an Non-volatile Memory Express (NVMe) bounce buffer in virtual memory that is associated with an NVMe command and perform an address translation to an NVMe bounce buffer based on receipt of a response to the NVMe command from an NVMe target. In some examples, the circuitry is to translate the virtual address to a physical address for the NVMe bounce buffer based on receipt of a response to the NVMe command from an NVMe target.

公开(公告)号：US20200278893A1

公开(公告)日：2020-09-03

申请号：US16814788

申请日：2020-03-10

Applicant: Intel Corporation

Inventor： Jose NIELL ,  Bradley A. BURRES ,  Kiel BOYLE ,  David NOELDNER ,  Keith SHAW ,  Karl P. BRUMMEL

IPC: G06F9/54 ,  G06F9/48 ,  G06F9/455 ,  G06F9/50 ,  H04L29/08 ,  G06F13/40 ,  G06F13/42

Abstract: Examples described herein relate to migrating a virtualized execution environment from a first platform to a second platform while retaining use of namespace identifiers and permitting issuance of storage transactions by the virtualized execution environment. The first platform can include a first central processing unit or a first network interface. The second platform can include a central processing unit that is different that the first central processing unit and a network interface that is the same or different than the first network interface. The second platform can retain access permissions and target media format independent of one or more identifiers associated with the migrated virtualized execution environment at the second platform. Unperformed storage transactions can be migrated to the second platform for execution.

公开(公告)号：US20220114030A1

公开(公告)日：2022-04-14

申请号：US17560881

申请日：2021-12-23

Applicant: Intel Corporation

Inventor： Salma Mirza JOHNSON ,  Jose NIELL ,  Bradley A. BURRES ,  Yadong LI ,  Scott D. PETERSON ,  Tony HURSON ,  Sujoy SEN

IPC: G06F9/50 ,  G06F9/4401 ,  G06F9/30 ,  G06F16/901

Abstract: Examples described herein relate to a network interface device that includes circuitry to perform operations, offloaded from a host, to identify at least one locator of at least one target storage associated with a storage access command based on operations selected from among multiple available operations, wherein the available operations comprise two or more: entry lookup by the network interface device, hash-based calculation on the network interface device, or control plane processing on the network interface device.

公开(公告)号：US20210019270A1

公开(公告)日：2021-01-21

申请号：US17030921

申请日：2020-09-24

Applicant: Intel Corporation

Inventor： Yadong LI ,  Jose NIELL ,  Kiel BOYLE

IPC: G06F13/16 ,  G06F13/42 ,  G06F9/50

Abstract: Examples described herein relate to a network interface controller apparatus, that includes a processor component comprising at least one processor to generate remote memory access communications to access a first group of one or more namespaces; storage interface circuitry to generate remote memory access communications to access a second group of one or more namespaces; and a storage configuration circuitry with a device interface that is accessible through a user space driver, the storage configuration circuitry to set the first and second group of one or more namespaces. In some examples, the device interface is compatible with Peripheral Component Interconnect Express (PCIe) and the storage configuration circuitry is accessible as a physical function (PF) or a virtual function (VF).

公开(公告)号：US20220113913A1

公开(公告)日：2022-04-14

申请号：US17560912

申请日：2021-12-23

Applicant: Intel Corporation

Inventor： Jose NIELL ,  Yadong LI ,  Salma Mirza JOHNSON ,  Scott D. PETERSON ,  Sujoy SEN

IPC: G06F3/06

Abstract: Examples described herein relate to a network interface device that includes circuitry to receive storage access command and determine a processing path in the network interface device for the storage access command, wherein the processing path is within the network interface device and wherein the processing path is selected from direct mapped or control plane processed based at least on command type and source of command. In some examples, the command type is read or write.

公开(公告)号：US20190207868A1

公开(公告)日：2019-07-04

申请号：US16276979

申请日：2019-02-15

Applicant: Intel Corporation

Inventor： Chih-Jen CHANG ,  Daniel Christian BIEDERMAN ,  Matthew James WEBB ,  Wing CHEUNG ,  Jose NIELL ,  Robert HATHAWAY

IPC: H04L12/927 ,  H04L12/851 ,  H04L12/721 ,  H04L12/24

CPC classification number: H04L47/805 ,  H04L41/042 ,  H04L45/38 ,  H04L47/2433 ,  H04L47/2483 ,  H04L2212/00

Abstract: A compute device can access local or remote accelerator devices for use in processing a received packet. The received packet can be processed by any combination of local accelerator devices and remote accelerator devices. In some cases, the received packet can be encapsulated in an encapsulating packet and sent to a remote accelerator device for processing. The encapsulating packet can indicate a priority level for processing the received packet and its associated processing task. The priority level can override a priority level that would otherwise be assigned to the received packet and its associated processing task. The remote accelerator device can specify a fullness of an input queue to the compute device. Other information can be conveyed by packets transmitted between and among compute devices and remote accelerator devices to assist in determining an accelerator to use or other uses.