公开(公告)号：US20230370241A1

公开(公告)日：2023-11-16

申请号：US18206027

申请日：2023-06-05

Applicant: Intel Corporation

Inventor： Daniel Christian BIEDERMAN ,  Mark BORDOGNA ,  Christopher S. HALL ,  James COLEMAN

IPC: H04L7/00

CPC classification number: H04L7/0008 ,  H04L7/0087

Abstract: Examples described herein relate to a in a group of servers: the servers attempting to perform timing synchronization based on a first group of timing signals sent via a first path. In some examples, the first comprises a first connection and based on disruption of communications by the first connection between servers in the group of servers. In some examples, the servers attempting to perform timing synchronization based on a second group of timing signals sent via a second path. In some examples, the second path does not traverse the first connection.

公开(公告)号：US20220309005A1

公开(公告)日：2022-09-29

申请号：US17214851

申请日：2021-03-27

Applicant: Intel Corporation

Inventor： Vedvyas SHANBHOGUE ,  Krishnakumar GANAPATHY ,  Venkateswara MADDURI ,  James ALLEN ,  James COLEMAN ,  Stephen ROBINSON

IPC: G06F12/0897 ,  G06F3/06

Abstract: Techniques for controlling bandwidth in a core are described. An exemplary core includes a memory bandwidth monitor per thread local to the core, each thread's local bandwidth monitor to at least allocate bandwidth for memory requests originating from the thread according to a class of service level stored in a field of quality of service (QoS) model-specific register (MSR), the class of service level pointed to by a class of service field in a platform quality of service MSR; and execution resources to support execution of at least one thread of the core.