公开(公告)号：US11307873B2

公开(公告)日：2022-04-19

申请号：US15944546

申请日：2018-04-03

Applicant: Intel Corporation

Inventor： Pablo Halpern ,  Kermin E. Fleming ,  James Sukha

IPC: G06F9/448 ,  G06F15/82

Abstract: Systems, methods, and apparatuses relating to unstructured data flow in a configurable spatial accelerator are described. In one embodiment, a configurable spatial accelerator includes a data path having a first branch and a second branch, and the data path comprises at least one processing element; a switch circuit comprising a switch control input to receive a first switch control value to couple an input of the switch circuit to the first branch and a second switch control value to couple the input of the switch circuit to the second branch; a pick circuit comprising a pick control input to receive a first pick control value to couple an output of the pick circuit to the first branch and a second pick control value to couple the output of the pick circuit to a third branch of the data path; a predicate propagation processing element to output a first edge predicate value and a second edge predicate value based on (e.g., both of) a switch control value from the switch control input of the switch circuit and a first block predicate value; and a predicate merge processing element to output a pick control value to the pick control input of the pick circuit and a second block predicate value based on both of a third edge predicate value and one of the first edge predicate value or the second edge predicate value.

公开(公告)号：US20190042217A1

公开(公告)日：2019-02-07

申请号：US15855964

申请日：2017-12-27

Applicant: Intel Corporation

Inventor： Kent Glossop ,  Kermin Fleming ,  Yongzhi Zhang ,  Simon Steely, JR. ,  James Sukha ,  Uma Srinivasan

IPC: G06F8/41

CPC classification number: G06F8/433 ,  G06F8/441 ,  G06F8/443 ,  G06F8/4441 ,  G06F8/447

Abstract: Methods, apparatus, systems and articles of manufacture to compiler compile code to generate dataflow code are described. An example compiler apparatus includes an intermediate representation transformer to transform input software code to intermediate representation code; an instruction selector to insert machine instructions of a target execution platform in the intermediate representation code to generate machine intermediate representation code; and a target machine transformer to: convert a portion of the machine intermediate representation code to dataflow code to generate dataflow intermediate representation code; and allocate registers within the dataflow intermediate representation code.