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    DEVICE, SYSTEM, AND METHOD TO CONCURRENTLY STORE MULTIPLE PMON COUNTS IN A SINGLE REGISTER
    3.
    发明申请
    DEVICE, SYSTEM, AND METHOD TO CONCURRENTLY STORE MULTIPLE PMON COUNTS IN A SINGLE REGISTER 有权

    公开(公告)号：US20220196733A1

    公开(公告)日：2022-06-23

    申请号：US17131477

    申请日：2020-12-22

    Applicant: Intel Corporation

    Inventor： Gaurav Porwal ,  Subhankar Panda ,  Theodros Yigzaw ,  John Holm

    IPC: G01R31/317

    Abstract: Techniques and mechanisms for providing performance monitoring information. In an embodiment, a performance monitor circuit receives a communication which indicates a format comprising multiple fields which are each to store a respective count of monitored events. A programming of the performance monitor circuit, based on the communication, designates first bits and second bits of the register to provide, respectively, a first first field and a second field according to the format. Performance monitoring subsequent to the programming successively tallies a first count of first events which occur during a first period of time, and a second count of second events which occur during a second period of time. In another embodiment, performance monitoring results in the register concurrently storing both the first count and the second count.

    Common architecture state presentation for processor having processing cores of different types
    4.
    发明授权
    Common architecture state presentation for processor having processing cores of different types 有权
    具有不同类型处理核心的处理器的通用架构状态表示

    公开(公告)号：US09367325B2

    公开(公告)日：2016-06-14

    申请号：US13931887

    申请日：2013-06-29

    Applicant: Intel Corporation

    Inventor： Bret Toll ,  Jason W. Brandt ,  John Holm

    IPC: G06F13/00 ,  G06F15/00 ,  G06F9/38

    CPC classification number: G06F9/3009 ,  G06F9/30098 ,  G06F9/3012 ,  G06F9/3851 ,  G06F9/3867 ,  G06F9/3891 ,  G06F9/46 ,  G06F15/80

    Abstract: A method is described that includes deciding to migrate a thread from a first processing core to a second processing core. The method also includes automatically in hardware migrating first context of the thread of the first processing core whose register definition is also found on the second processing core to the second processing core. The method also includes automatically in hardware migrating second context of the thread of the first processing core whose register definition is not found on the second processing core to a first storage location external to the second processing core. The message also includes automatically in hardware migrating third context of the thread from a second storage location external to the second processing core to register definition found on the second processing core but not found on the first processing core.

    Abstract translation: 描述了一种方法，其包括决定将线程从第一处理核心迁移到第二处理核心。 该方法还自动地将第一处理核心的线程的第一上下文自动迁移到其第二处理核心的第二处理核心上也将其寄存器定义也被发现。 该方法还自动地将在第二处理核心上没有发现其寄存器定义的第一处理核心的线程的第二上下文迁移到第二处理核心外部的第一存储位置。 消息还自动地包括将线程的第三上下文从第二处理核心外部的第二存储位置迁移到在第二处理核心上找到但在第一处理核心上找不到的寄存器定义的硬件。

    FIRMWARE FIRST HANDLING OF A MACHINE CHECK EVENT
    5.
    发明公开
    FIRMWARE FIRST HANDLING OF A MACHINE CHECK EVENT 审中-公开

    公开(公告)号：US20230315575A1

    公开(公告)日：2023-10-05

    申请号：US17711465

    申请日：2022-04-01

    Applicant: Intel Corporation

    Inventor： Sarathy Jayakumar ,  Eswar Konduru ,  John Holm

    IPC: G06F11/14 ,  G06F9/445 ,  G06F21/57

    CPC classification number: G06F11/142 ,  G06F9/445 ,  G06F21/572 ,  G06F2221/033 ,  G06F2201/805

    Abstract: Techniques and mechanisms for supporting machine check functionality with a handler which is implemented in firmware. In an embodiment, a processor executes first firmware code to implement a machine check event (MCE) detector. The MCE detector detects a hardware error of a platform which includes the processor, and generates a call to invoke an MCE handler which the processor implements by executing second firmware code. The MCE handler is called, outside of a software context, to attempt a recovery from the hardware error. The call is performed independent of any system management interrupt being based on the detected hardware error. In another embodiment, another MCE handler of an operating system is conditionally invoked where it is determined that the attempted recovery by the first MCE handler was unsuccessful.

    Device, system, and method to concurrently store multiple PMON counts in a single register
    6.
    发明授权
    Device, system, and method to concurrently store multiple PMON counts in a single register 有权

    公开(公告)号：US12044730B2

    公开(公告)日：2024-07-23

    申请号：US17131477

    申请日：2020-12-22

    Applicant: Intel Corporation

    Inventor： Gaurav Porwal ,  Subhankar Panda ,  Theodros Yigzaw ,  John Holm

    IPC: G01R31/28 ,  G01R31/317

    CPC classification number: G01R31/317

    Abstract: Techniques and mechanisms for providing performance monitoring information. In an embodiment, a performance monitor circuit receives a communication which indicates a format comprising multiple fields which are each to store a respective count of monitored events. A programming of the performance monitor circuit, based on the communication, designates first bits and second bits of the register to provide, respectively, a first first field and a second field according to the format. Performance monitoring subsequent to the programming successively tallies a first count of first events which occur during a first period of time, and a second count of second events which occur during a second period of time. In another embodiment, performance monitoring results in the register concurrently storing both the first count and the second count.

    Hardware unit for reverse translation in a processor
    7.
    发明授权
    Hardware unit for reverse translation in a processor 有权

    公开(公告)号：US11307996B2

    公开(公告)日：2022-04-19

    申请号：US16206516

    申请日：2018-11-30

    Applicant: Intel Corporation

    Inventor： Sarathy Jayakumar ,  Ashok Raj ,  Wei P. Chen ,  Theodros Yigzaw ,  John Holm

    IPC: G06F12/1027 ,  G06F12/0864 ,  G06F13/16 ,  G06F11/22 ,  G06F9/38

    Abstract: In an embodiment, a processor for reverse translation includes a plurality of processing engines (PEs) to execute threads and a reverse translation circuit. The reverse translation circuit is to: determine a target module address of a corrupt portion of a memory module; determine a plurality of system physical address (SPA) addresses associated with the memory module; and for each SPA address in the plurality of SPA addresses, translate the SPA address into a translated module address, and in response to a determination that the translated module address matches the target module address, log the SPA address as a result of a reverse translation of the target module address. Other embodiments are described and claimed.

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