公开(公告)号：US11989106B2

公开(公告)日：2024-05-21

申请号：US16711243

申请日：2019-12-11

Applicant: Intel Corporation

Inventor： Jongwon Lee ,  Kuljit S. Bains

IPC: G06F11/20 ,  G06F12/0875 ,  G06F12/10 ,  G11C11/4091 ,  G11C29/44 ,  G11C11/408

CPC classification number: G06F11/2094 ,  G06F12/0875 ,  G06F12/10 ,  G11C11/4091 ,  G11C29/4401 ,  G06F2201/82 ,  G06F2212/45 ,  G11C11/4085

Abstract: In a memory system, a memory device has a memory array with multiple rows of memory having logical addresses mapped to their physical addresses and at least one spare row not having a logical address mapped to its physical address. A controller detects a failure of one of the multiple rows of memory (“failure row”) and executes a post package repair (PPR) mode. The controller can be internal to the memory device or external to the memory device. The memory device includes an internal scratchpad to allow transfer of data contents from the failure row to the spare row. The controller can map the logical address of the failure row from the physical address of the failure row to the physical address of the spare row, transfer data contents from the failure row to the internal scratchpad, and transfer the data contents from the internal scratchpad to the spare row.

公开(公告)号：US11144466B2

公开(公告)日：2021-10-12

申请号：US16433663

申请日：2019-06-06

Applicant: Intel Corporation

Inventor： Jongwon Lee ,  Vivek Kozhikkottu ,  Kuljit S. Bains ,  Hussein Alameer

IPC: G06F12/0882 ,  G11C7/10

Abstract: An embodiment of a memory device includes technology for a memory cell array logically organized in two or more banks of at least two rows and two columns per bank, and two or more local caches respectively coupled to the two or more banks of the memory cell array, where each local cache has a size which is an integer multiple of a memory page size of the memory cell array. Other embodiments are disclosed and claimed.

公开(公告)号：US20190286566A1

公开(公告)日：2019-09-19

申请号：US16433663

申请日：2019-06-06

Applicant: Intel Corporation

Inventor： Jongwon Lee ,  Vivek Kozhikkottu ,  Kuljit S. Bains ,  Hussein Alameer

IPC: G06F12/0882 ,  G11C7/10

Abstract: An embodiment of a memory device includes technology for a memory cell array logically organized in two or more banks of at least two rows and two columns per bank, and two or more local caches respectively coupled to the two or more banks of the memory cell array, where each local cache has a size which is an integer multiple of a memory page size of the memory cell array. Other embodiments are disclosed and claimed.

公开(公告)号：US11966286B2

公开(公告)日：2024-04-23

申请号：US17715771

申请日：2022-04-07

Applicant: Intel Corporation

Inventor： Kuljit S. Bains ,  Rajat Agarwal ,  Jongwon Lee

IPC: G06F11/10 ,  G11C11/4096

CPC classification number: G06F11/1044 ,  G06F11/1072 ,  G11C11/4096

Abstract: A memory device that performs internal ECC (error checking and correction) can selectively return read data with application of the internal ECC or without application of the internal ECC, in response to different read commands from the memory controller. The memory device can normally apply ECC and return corrected data in response to a normal read command. In response to a retry command, the memory device can return the read data without application of the internal ECC.

公开(公告)号：US11314589B2

公开(公告)日：2022-04-26

申请号：US16875642

申请日：2020-05-15

Applicant: Intel Corporation

Inventor： Kuljit S. Bains ,  Rajat Agarwal ,  Jongwon Lee

IPC: G06F11/10 ,  G11C11/4096

Abstract: A memory device that performs internal ECC (error checking and correction) can selectively return read data with application of the internal ECC or without application of the internal ECC, in response to different read commands from the memory controller. The memory device can normally apply ECC and return corrected data in response to a normal read command. In response to a retry command, the memory device can return the read data without application of the internal ECC.

公开(公告)号：US12164373B2

公开(公告)日：2024-12-10

申请号：US17339754

申请日：2021-06-04

Applicant: Intel Corporation

Inventor： Bill Nale ,  Kuljit S. Bains ,  Lawrence Blankenbeckler ,  Ronald Anderson ,  Jongwon Lee

IPC: G06F11/00 ,  G06F11/10 ,  G11C11/406 ,  G11C11/4096

Abstract: A memory chip is described. The memory chip includes storage cells along a row of the memory chip's storage cell array to store a count value of the row's activations and error correction code (ECC) information to protect the count value. The memory chip includes ECC read logic circuitry to correct an error in the count value. The memory chip includes a comparator to compare the count value against a threshold. The memory chip includes circuitry to increment the count value if the count value is deemed not to have reached the threshold and ECC write logic circuitry to determine new ECC information for the incremented count value, and write driver circuitry to write the incremented count value and the new ECC information into the storage cells. The memory chip includes circuitry to cause the row to be refreshed if the count value is deemed to have reached the threshold.