公开(公告)号：US20220012206A1

公开(公告)日：2022-01-13

申请号：US17484768

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Kevin BROSS ,  Benjamin CHEONG ,  Danae A. BERGE ,  April E. FISHER

IPC: G06F13/40 ,  G06F13/42

Abstract: An adaptor is described. The adaptor includes a first interface. The first interface is designed to support traffic and command flows to multiple transceivers through a single instance of the first interface. The adaptor includes multiple interfaces on a transceiver side. The multiple interfaces are to mate to respective transceivers. The multiple interfaces are different than the first interface, wherein the first interface is a QSFP interface and the multiple interfaces are SFP interfaces. The adaptor includes a flex cable between the first interface and the multiple interfaces. The adaptor includes electronic circuitry to translate QSFP commands received at the first interface into SFP commands presented to the respective transceivers through the multiple interfaces.

公开(公告)号：US20200266967A1

公开(公告)日：2020-08-20

申请号：US16783077

申请日：2020-02-05

Applicant: Intel Corporation

Inventor： April E. FISHER ,  Benjamin CHEONG ,  Kevin BROSS ,  Manishkumar T. RANA ,  Andrew M. MONK

IPC: H04L7/00

Abstract: Examples described herein are used in timing synchronization systems. A timing synchronization system provides circuits that support bi-directional half-duplex voltage signals (transmit or receive) but protect against incorrect input/output configuration whereby a transmit signal media is connected to a receive port or a receive signal media is connected to a transmit port. The system provides configurable signal propagation by use of parallel connection of two or more buffer in series with a resistor. Various isolation circuitry and resistors can be used to protect against signal transmission during receive mode.