公开(公告)号：US20220116325A1

公开(公告)日：2022-04-14

申请号：US17560110

申请日：2021-12-22

Applicant: Intel Corporation

Inventor： Bruce G. WARREN ,  Robert ZAK ,  Mark DEBBAGE ,  Todd RIMMER

IPC: H04L45/745 ,  H04L69/22

Abstract: Examples described herein relate to a network interface device that includes circuitry to decide packet format of a packet including data to be transmitted based on network utilized to transmit the packet and circuitry to form the packet based on the decided packet format. In some examples, the network utilized to transmit the packet is based on an egress port of the packet. In some examples, the network utilized to transmit the packet comprises one or more of: direct interconnect, small scale-up network, or large scale-out network. In some examples, to decide packet format, the circuitry is to form the packet byte by byte to reduce overhead caused by preamble and number of header fields.

公开(公告)号：US20220124035A1

公开(公告)日：2022-04-21

申请号：US17561839

申请日：2021-12-24

Applicant: Intel Corporation

Inventor： Junggun LEE ,  Jeremias BLENDIN ,  Yanfang LE ,  Rong PAN ,  Mark DEBBAGE ,  Robert SOUTHWORTH

IPC: H04L47/12 ,  H04L47/2483 ,  H04L43/0817 ,  H04L43/0882 ,  H04L43/0888

Abstract: Examples described herein relate to a switch circuitry that includes circuitry to determine if a received packet comprises a control packet; circuitry to determine congestion metrics based on receipt of at least one control packet, wherein the at least one control packet comprises a Request To Send (RTS) or Clear To Send (CTS); and circuitry to transmit at least one of the congestion metrics in at least one packet to a sender and/or receiver network interface device.

公开(公告)号：US20220085916A1

公开(公告)日：2022-03-17

申请号：US17483668

申请日：2021-09-23

Applicant: Intel Corporation

Inventor： Mark DEBBAGE ,  Bruce G. WARREN

IPC: H04L1/16 ,  H04L69/22 ,  H04L49/90

Abstract: Examples described herein relate to a network interface device that includes circuitry to track one or more gaps in received packet sequence numbers using data and circuitry to indicate to a sender of packets non-delivered packets to identify a range of delivered packets. In some examples, the data identifies delivered packets and undelivered packets for one or more connections. In some examples, to indicate to a sender of packets non-delivered packets to identify a range of delivered packets, the circuitry is to provide negative acknowledgement sequence range indicating a start and end of non-delivered packets.

公开(公告)号：US20210119930A1

公开(公告)日：2021-04-22

申请号：US17084526

申请日：2020-10-29

Applicant: Intel Corporation

Inventor： Mark DEBBAGE ,  Robert SOUTHWORTH ,  Arvind SRINIVASAN ,  Cheolmin PARK ,  Todd RIMMER ,  Brian S. HAUSAUER

IPC: H04L12/801 ,  H04L12/803 ,  H04L1/16

Abstract: Examples described herein relate to technologies for reliable packet transmission. In some examples, a network interface includes circuitry to: receive a request to transmit a packet to a destination device, select a path for the packet, provide a path identifier identifying one of multiple paths from the network interface to a destination and Path Sequence Number (PSN) for the packet, wherein the PSN is to identify a packet transmission order over the selected path, include the PSN in the packet, and transmit the packet. In some examples, if the packet is a re-transmit of a previously transmitted packet, the circuitry is to: select a path for the re-transmit packet, and set a PSN of the re-transmit packet that is a current packet transmission number for the selected path for the re-transmit packet. In some examples, a network interface includes circuitry to process a received packet to at least determine a Path Sequence Number (PSN) for the received packet, wherein the PSN is to provide an order of packet transmissions for a path associated with the received packet, process a second received packet to at least determine its PSN, and based on the PSN of the second received packet not being a next sequential value after the PSN of the received packet, cause transmission of a re-transmit request to a sender of the packet and the second packet.

公开(公告)号：US20220351326A1

公开(公告)日：2022-11-03

申请号：US17853711

申请日：2022-06-29

Applicant: Intel Corporation

Inventor： Todd RIMMER ,  Mark DEBBAGE ,  Bruce G. WARREN ,  Sayantan SUR ,  Nayan Amrutlal SUTHAR ,  Ajaya Durg

IPC: G06T1/20 ,  G06T1/60

Abstract: Examples described herein relate to a first graphics processing unit (GPU) with at least one integrated communications system, wherein the at least one integrated communications system is to apply a reliability protocol to communicate with a second at least one integrated communications system associated with a second GPU to copy data from a first memory region to a second memory region and wherein the first memory region is associated with the first GPU and the second memory region is associated with the second GPU.

公开(公告)号：US20220138021A1

公开(公告)日：2022-05-05

申请号：US17561903

申请日：2021-12-24

Applicant: Intel Corporation

Inventor： Todd RIMMER ,  Mark DEBBAGE

IPC: G06F9/50 ,  G06F15/173

Abstract: Examples described herein relate to a sender process having a capability to select from use of a plurality of connections to at least one target process, wherein the plurality of connections to at least one target process comprise a connection for the sender process and/or one or more connections allocated per job. In some examples, the connection for the sender process comprises a datagram transport for message transfers. In some examples, the one or more connections allocated per job utilize a kernel bypass datagram transport for message transfers. In some examples, the one or more connections allocated per job comprise a connection oriented transport and wherein multiple remote direct memory access (RDMA) write operations for a plurality of processes are to be multiplexed using the connection oriented transport.

公开(公告)号：US20220124046A1

公开(公告)日：2022-04-21

申请号：US17561840

申请日：2021-12-24

Applicant: Intel Corporation

Inventor： Mark DEBBAGE

IPC: H04L47/31 ,  H04L67/1097 ,  H04L69/00

Abstract: Examples described herein relate to a network interface device performing offloaded tag matching operation to support both one or more eager transactions and one or more rendezvous transactions using a tag-matching protocol. In some examples, the tag matching operation is offloaded from a server to the network interface device. In some examples, the network interface device is to receive messages from one or more senders, wherein the messages comprise tags and select one or more of the messages to write into a buffer based on matching on sender and/or tag.