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    CACHE ALLOCATION SYSTEM
    1.
    发明申请
    CACHE ALLOCATION SYSTEM 有权

    公开(公告)号：US20210359955A1

    公开(公告)日：2021-11-18

    申请号：US17384627

    申请日：2021-07-23

    Applicant: Intel Corporation

    Inventor： Malek MUSLEH ,  Tony HURSON ,  Pedro YEBENES SEGURA ,  Allister ALEMANIA ,  Roberto PENARANDA CEBRIAN ,  Ayan BANERJEE ,  Robert SOUTHWORTH ,  Sujoy SEN ,  Curt E. BRUNS

    IPC: H04L12/911 ,  H04L12/923 ,  H04L12/927 ,  G06F15/173

    Abstract: Examples described herein relate to a network interface device comprising: a host interface, a direct memory access (DMA) engine, and circuitry to allocate a region in a cache to store a context of a connection. In some examples, the circuitry is to allocate a region in a cache to store a context of a connection based on connection reliability and wherein connection reliability comprises use of a reliable transport protocol or non-use of a reliable transport protocol. In some examples, the circuitry is to allocate a region in a cache to store a context of a connection based on expected length of runtime of the connection and the expected length of runtime of the connection is based on a historic average amount of time the context for the connection was stored in the cache. In some examples, the circuitry is to allocate a region in a cache to store a context of a connection based on content transmitted and the content transmitted comprises congestion messaging payload or acknowledgement. In some examples, the circuitry is to allocate a region in a cache to store a context of a connection based on application-specified priority level and the application-specified priority level comprises an application-specified traffic class level or class of service level.

    PROGRAMMABLE TRANSPORT PROTOCOL ARCHITECTURE
    2.
    发明申请
    PROGRAMMABLE TRANSPORT PROTOCOL ARCHITECTURE 有权

    公开(公告)号：US20230127722A1

    公开(公告)日：2023-04-27

    申请号：US18089486

    申请日：2022-12-27

    Applicant: Intel Corporation

    Inventor： Stephen IBANEZ ,  Robert SOUTHWORTH ,  Salma Mirza JOHNSON ,  Vered BAR BRACHA ,  Bradley A. BURRES

    IPC: G06F9/54 ,  G06F9/48

    Abstract: Examples described herein relate to a network interface device that includes a programmable event processing architecture that includes a plurality of programmable event processors. In some examples, the plurality of programmable event processors are to perform memory accesses separate from compute operations. In some examples, the plurality of programmable event processors are to group one or more events into at least one group. In some examples, the plurality of programmable event processors are to perform parallel processing of events belonging to different groups. In some examples, the plurality of programmable event processors are programmed to perform at least one transport protocol.

    PROGRAMMABLE ARCHITECTURE FOR STATEFUL DATA PLANE EVENT PROCESSING
    5.
    发明申请
    PROGRAMMABLE ARCHITECTURE FOR STATEFUL DATA PLANE EVENT PROCESSING 有权

    公开(公告)号：US20230139762A1

    公开(公告)日：2023-05-04

    申请号：US18089453

    申请日：2022-12-27

    Applicant: Intel Corporation

    Inventor： Stephen IBANEZ ,  Robert SOUTHWORTH ,  Salma Mirza JOHNSON ,  Vered BAR BRACHA ,  Bradley A. BURRES

    IPC: G06F9/50 ,  G06F9/54 ,  G06F9/52

    Abstract: Examples described herein relate to a network interface device that includes a programmable event processing architecture comprising a plurality of programmable event processors. When the plurality of programmable event processors are operational, one or more of the programmable event processors are to perform memory accesses separate from compute operations, group one or more events into at least one group, enforce atomic processing of other events within a group of the at least one group, wherein the atomic processing comprises propagation of state changes to among events of the group, and perform parallel processing of events belonging to different groups.

    WINDOW-BASED CONGESTION CONTROL
    6.
    发明申请
    WINDOW-BASED CONGESTION CONTROL 有权

    公开(公告)号：US20230123387A1

    公开(公告)日：2023-04-20

    申请号：US18082749

    申请日：2022-12-16

    Applicant: Intel Corporation

    Inventor： Robert SOUTHWORTH ,  Rong PAN ,  Tony HURSON ,  Siqi LIU

    IPC: H04L47/122 ,  H04L47/56 ,  H04L45/00

    Abstract: Examples described herein relate to a network interface device that includes circuitry to cause transmission of a packet following transmission of one or more data packets to a receiver, wherein the packet comprises one or more of: a count of transmitted data, a timestamp of transmission of the packet, and/or an index value to one or more of a count of transmitted data and a timestamp of transmission of the packet. In some examples, the network interface device includes circuitry to receive, from the receiver, a second packet that includes a copy of the count of transmitted data and the timestamp of transmission of the packet or the index from the packet. In some examples, the network interface device includes circuitry to perform congestion control based on the received copy of the count of transmitted data and the timestamp of transmission of the packet.

    ACCELERATING MULTI-NODE PERFORMANCE OF MACHINE LEARNING WORKLOADS
    7.
    发明申请
    ACCELERATING MULTI-NODE PERFORMANCE OF MACHINE LEARNING WORKLOADS 有权

    公开(公告)号：US20210092069A1

    公开(公告)日：2021-03-25

    申请号：US17118409

    申请日：2020-12-10

    Applicant: Intel Corporation

    Inventor： Malek MUSLEH ,  Anupama KURPAD ,  Roberto PENARANDA CEBRIAN ,  Allister ALEMANIA ,  Pedro YEBENES SEGURA ,  Curt E. BRUNS ,  Robert SOUTHWORTH ,  Sujoy SEN

    IPC: H04L12/851 ,  H04L12/751 ,  H04L12/853 ,  H04L12/727 ,  G06N3/08 ,  G06N3/04

    Abstract: Examples described herein relate to a network interface and at least one processor that is to indicate whether data is associated with a machine learning operation or non-machine learning operation to manage traversal of the data through one or more network elements to a destination network element and cause the network interface to include an indication in a packet of whether the packet includes machine learning data or non-machine learning data. In some examples, the indication in a packet of whether the packet includes machine learning data or non-machine learning data comprises a priority level and wherein one or more higher priority levels identify machine learning data. In some examples, for machine learning data, the priority level is based on whether the data is associated with inference, training, or re-training operations. In some examples, for machine learning data, the priority level is based on whether the data is associated with real-time or time insensitive inference operations.

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