公开(公告)号：US09766678B2

公开(公告)日：2017-09-19

申请号：US13758897

申请日：2013-02-04

Applicant: Intel Corporation

Inventor： Ramnarayanan Muthukaruppan ,  Harish K. Krishnamurthy ,  Mohit Verma ,  Pradipta Patra ,  Uday Bhaskar Kadali

IPC: G06F9/00 ,  G06F1/32

CPC classification number: G06F1/32 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3296 ,  Y02D10/152 ,  Y02D10/172

Abstract: Described is an apparatus comprising: first and second processing cores; and a PCU which is operable to: generate a first VID for an off-die regulator external to the apparatus, the first VID resulting in a first power supply for the first processing core; and generate a second VID different from the first VID, the second VID resulting in a second power supply for the second processing core. Described is an apparatus comprising: a plurality of power-gate transistors controllable by a digital bus, the plurality of power-gate transistors operable to provide a first power supply to a processing core, and to receive a second power supply as input; an ADC to receive the first power supply and to generate a digital output representative of the first power supply; and a controller to receive the digital output representative and to generate the digital bus for controlling the plurality of power-gate transistors.

公开(公告)号：US10469214B1

公开(公告)日：2019-11-05

申请号：US16219441

申请日：2018-12-13

Applicant: Intel Corporation

Inventor： Pankaj Dudulwar ,  Mohit Verma ,  Hongjiang Song ,  Mingming Xu

IPC: H04L1/20 ,  H03L7/07 ,  G01R31/317

Abstract: Techniques and mechanisms for a clock recovery circuit to generate a cyclical signal based on data signals which are susceptible to circuit switching jitter. In an embodiment, a clock recovery circuit comprises switch circuitry which receives a first signal representing a logical combination of multiple pulsed signals (which, in turn, are each based on a different respective differential data signal). The switch circuitry provides to latch circuitry of the clock recovery circuit a second signal based on the first signal. The latch circuitry generates a cyclical signal based on the second signal, and transitions the switch circuitry between an open-circuit state and a closed-circuit state. In another embodiment, the latch circuitry implements a predetermined and configurable time period between a transition of the cyclical signal and a next subsequent logic state transition of the cyclical signal.

公开(公告)号：US10185382B2

公开(公告)日：2019-01-22

申请号：US15292067

申请日：2016-10-12

Applicant: Intel Corporation

Inventor： Ramnarayanan Muthukaruppan ,  Harish K. Krishnamurthy ,  Mohit Verma ,  Pradipta Patra ,  Uday Bhaskar Kadali

IPC: G06F1/00 ,  G06F1/32

Abstract: Described is an apparatus comprising: first and second processing cores; and a PCU which is operable to: generate a first VID for an off-die regulator external to the apparatus, the first VID resulting in a first power supply for the first processing core; and generate a second VID different from the first VID, the second VID resulting in a second power supply for the second processing core. Described is an apparatus comprising: a plurality of power-gate transistors controllable by a digital bus, the plurality of power-gate transistors operable to provide a first power supply to a processing core, and to receive a second power supply as input; an ADC to receive the first power supply and to generate a digital output representative of the first power supply; and a controller to receive the digital output representative and to generate the digital bus for controlling the plurality of power-gate transistors.

公开(公告)号：US10345881B2

公开(公告)日：2019-07-09

申请号：US15653764

申请日：2017-07-19

Applicant: Intel Corporation

Inventor： Ramnarayanan Muthukaruppan ,  Harish K. Krishnamurthy ,  Mohit Verma ,  Pradipta Patra ,  Uday Bhaskar Kadali

IPC: G06F9/00 ,  G06F1/32 ,  G06F1/3234 ,  G06F1/3296 ,  G06F1/324

Abstract: Described is an apparatus comprising: first and second processing cores; and a PCU which is operable to: generate a first VID for an off-die regulator external to the apparatus, the first VID resulting in a first power supply for the first processing core; and generate a second VID different from the first VID, the second VID resulting in a second power supply for the second processing core. Described is an apparatus comprising: a plurality of power-gate transistors controllable by a digital bus, the plurality of power-gate transistors operable to provide a first power supply to a processing core, and to receive a second power supply as input; an ADC to receive the first power supply and to generate a digital output representative of the first power supply; and a controller to receive the digital output representative and to generate the digital bus for controlling the plurality of power-gate transistors.