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公开(公告)号：US09559878B2
公开(公告)日：2017-01-31
申请号：US15019835
申请日：2016-02-09
Applicant: Intel Corporation
Inventor： Stefano Giaconi , Mingming Xu
CPC classification number: H04L25/03057 , H04L7/0041 , H04L7/0058 , H04L7/033 , H04L7/0331 , H04L7/0332 , H04L7/0334 , H04L25/03025 , H04L2025/03598
Abstract: Described are phase adjustment circuits for clock and data recovery circuits (CDRs). Systems and apparatuses may include an input to receive a serial data signal, an edge data tap to sample transition edges in the serial data signal for generating a data edge detection signal, a CDR circuit including a phase detector to receive the serial data signal and the data edge detection signal, and to output a phase lead/lag signal indicating the phase difference between the serial data signal and the data edge detection signal, and a phase adjustment circuit to generate phase lead/lag adjustment data. The CDR circuit is to output a recovered clock signal based, at least in part, on the phase lead/lag signal adjusted by the phase lead/lag adjustment data.
Abstract translation: 描述了时钟和数据恢复电路（CDR）的相位调整电路。 系统和装置可以包括用于接收串行数据信号的输入端，边缘数据抽头以对串行数据信号中的过渡边缘进行采样以产生数据边缘检测信号; CDR电路，包括用于接收串行数据信号的相位检测器和 数据边缘检测信号，并输出指示串行数据信号和数据边缘检测信号之间的相位差的相位超前/滞后信号，以及产生相位超前/滞后调整数据的相位调整电路。 CDR电路至少部分地基于由相位超前/滞后调整数据调整的相位超前/滞后信号来输出恢复的时钟信号。
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2.发明授权公开(公告)号：US12066959B2
公开(公告)日：2024-08-20
申请号：US17743297
申请日：2022-05-12
Applicant: Intel Corporation
Inventor： Vijayalakshmi Ramachandran , Mingming Xu , Dror Lazar
CPC classification number: G06F13/20 , G01R31/2889 , G05F1/46 , G06F2213/40
Abstract: Techniques and mechanisms for determining a reference voltage which is to be provided with an integrated circuit (IC) die. In an embodiment, the IC die comprises a resistor, and a hardware interface which accommodates coupling of the IC die to a test unit. The test unit provides functionality to perform an evaluation of a resistance of the resistor, wherein said resistance is indicative of the respective resistances of one or more other resistors of the IC die. Based on the evaluation, the test unit provides to the IC die an indication of a scale factor, wherein the reference voltage is generated based on the scale factor. In another embodiment, the IC die further comprises an amplifier circuit which receives the reference voltage, wherein a variable resistance circuit of the IC die is configured based on an output of the amplifier circuit.
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公开(公告)号：US09922248B2
公开(公告)日：2018-03-20
申请号：US14865401
申请日：2015-09-25
Applicant: Intel Corporation
Inventor： Mingming Xu , Stefano Giaconi , Wei Wang
CPC classification number: G06K9/0053 , G01R13/02 , G06K9/00503 , G06K9/00557 , G06K9/00604
Abstract: Some embodiments include apparatuses and methods having a receiver unit included in a die and a measurement unit included in the die. The receiver unit includes a sampler to sample a first signal based on timing of a first clock signal to generate a second signal. The measurement unit is arranged to sample the first signal based on timing of a second clock signal to provide information for generation of a graph presenting an eye scan of the first signal. The second clock signal has a frequency asynchronous with a frequency of the first clock signal.
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Patent Agency Ranking
公开(公告)号：US20230244525A1
公开(公告)日：2023-08-03
申请号：US18160209
申请日：2023-01-26
Applicant: Intel Corporation
Inventor： Ningxin Hu , Feng Dai , Junyong Ding , Junwei Fu , Mohammad Haghighat , Mousumi Hazra , Mingming Xu , Min Zhang
CPC classification number: G06F9/4881 , G06N5/022
Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for an XPU-aware dynamic compute scheduling framework. These improve processing of cloud client application pipelines across XPU devices by incorporating memory, machine readable instructions and processor circuitry to execute the functions of: trace an execution of an input model by a graph tracer; build a compute graph based on the trace of the input model; communicate an operational parameter; create a first XPU device assignment to recommend an XPU device to use based on at least one provisioned policy of a system-wide XPU selection policy provider; update the compute graph based on the first XPU device assignment; and send the first XPU device assignment to the devices through a dispatch command.
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公开(公告)号：US10469214B1
公开(公告)日：2019-11-05
申请号：US16219441
申请日：2018-12-13
Applicant: Intel Corporation
Inventor： Pankaj Dudulwar , Mohit Verma , Hongjiang Song , Mingming Xu
IPC: H04L1/20 , H03L7/07 , G01R31/317
Abstract: Techniques and mechanisms for a clock recovery circuit to generate a cyclical signal based on data signals which are susceptible to circuit switching jitter. In an embodiment, a clock recovery circuit comprises switch circuitry which receives a first signal representing a logical combination of multiple pulsed signals (which, in turn, are each based on a different respective differential data signal). The switch circuitry provides to latch circuitry of the clock recovery circuit a second signal based on the first signal. The latch circuitry generates a cyclical signal based on the second signal, and transitions the switch circuitry between an open-circuit state and a closed-circuit state. In another embodiment, the latch circuitry implements a predetermined and configurable time period between a transition of the cyclical signal and a next subsequent logic state transition of the cyclical signal.
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公开(公告)号：US09473259B2
公开(公告)日：2016-10-18
申请号：US14550822
申请日：2014-11-21
Applicant: INTEL CORPORATION
Inventor： Itamar Levin , Kevan A. Lillie , Dima Hammed , Elior Segev , Mingming Xu , Tomer Fael
CPC classification number: H04B17/24 , G06F11/221 , H04B17/00 , H04B17/29 , H04L25/03057 , H04L25/03146 , H04L25/03878
Abstract: Various embodiments are generally directed to techniques for testing a receiver incorporated into an IC to receive a bitstream. An apparatus includes a precharge component to set a VGA to output a differential bias voltage; a taps component to set a tap to form a feedback loop that extends from an output of the bit slicer to the input of the bit slicer through a delay circuit and the tap, the tap to output a first differential voltage to the input of the bit slicer to invert a polarity of a sum of differential voltages at the input of the bit slicer to enable oscillation of the bit slicer, the sum generated from at least the differential bias voltage and the first differential voltage; and a capture component coupled to the output of the bit slicer to capture a series of bit values therefrom. Other embodiments are described and claimed.
Abstract translation: 各种实施例通常涉及用于测试结合到IC中以接收比特流的接收机的技术。 一种装置包括：预充电部件，用于设置VGA以输出差分偏置电压; 抽头分量，用于设置抽头以形成反馈环路，该反馈环路通过延迟电路和抽头从位限幅器的输出延伸到位限幅器的输入，该抽头将第一差分电压输出到位的输入端 切片器，以在位限幅器的输入处反转差分电压之和的极性，以使得位限幅器的振荡，至少从差分偏置电压和第一差分电压产生的和; 以及耦合到所述位限幅器的输出以从其捕获一系列位值的捕获元件。 描述和要求保护其他实施例。
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公开(公告)号：US20240022254A1
公开(公告)日：2024-01-18
申请号：US17864593
申请日：2022-07-14
Applicant: Intel Corporation
Inventor： Hongjiang Song , Mingming Xu , Vijayalakshmi Ramachandran
Abstract: An apparatus, system, and method for low frequency periodic signaling (LFPS) and/or squelch detection are provided. A circuit can include a threshold generator situated to receive a differential input signal from an initiator device and generate a differential voltage threshold signal based on the differential input signal, an amplifier circuit electrically coupled to the threshold generator situated to amplify the differential voltage threshold signal resulting in an amplified threshold signal, a sampler situated to sample the amplified threshold signal at a first clock rate faster than a clock rate of an LFPS/squelch signaling frequency resulting in digital sample results, and a pattern filter circuit situated to determine if the digital sample results are asserted for each of a specified number of consecutive clock cycles at the first clock rate.
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8.发明公开公开(公告)号：US20230367725A1
公开(公告)日：2023-11-16
申请号：US17743297
申请日：2022-05-12
Applicant: Intel Corporation
Inventor： Vijayalakshmi Ramachandran , Mingming Xu , Dror Lazar
CPC classification number: G06F13/20 , G01R31/2889 , G05F1/46 , G06F2213/40
Abstract: Techniques and mechanisms for determining a reference voltage which is to be provided with an integrated circuit (IC) die. In an embodiment, the IC die comprises a resistor, and a hardware interface which accommodates coupling of the IC die to a test unit. The test unit provides functionality to perform an evaluation of a resistance of the resistor, wherein said resistance is indicative of the respective resistances of one or more other resistors of the IC die. Based on the evaluation, the test unit provides to the IC die an indication of a scale factor, wherein the reference voltage is generated based on the scale factor. In another embodiment, the IC die further comprises an amplifier circuit which receives the reference voltage, wherein a variable resistance circuit of the IC die is configured based on an output of the amplifier circuit.
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