公开(公告)号：US20230418750A1

公开(公告)日：2023-12-28

申请号：US17852189

申请日：2022-06-28

Applicant: Intel Corporation

Inventor： Yedidya Hilewitz ,  Monam Agarwal ,  Yen-Cheng Liu ,  Alexander Heinecke

IPC: G06F12/0815 ,  G06F12/0811 ,  G06F12/084

CPC classification number: G06F12/0815 ,  G06F12/0811 ,  G06F12/084

Abstract: Techniques for hierarchical core valid tracking are described. An example apparatus comprises a cache to store information accessible by two or more cores, and circuitry coupled to the cache to maintain coherence of the information stored in the cache and to hierarchically track respective associations of the information stored in the cache with the two or more cores, where a lowest hierarchical level of the hierarchically tracked associations is to indicate a logical core identifier of a particular core of the two or more cores. Other examples are disclosed and claimed.

公开(公告)号：US11860670B2

公开(公告)日：2024-01-02

申请号：US17553458

申请日：2021-12-16

Applicant: Intel Corporation

Inventor： Monam Agarwal ,  Anand K. Enamandram ,  Wei Chen ,  Kerry Vander Kamp ,  Robert A. Branch ,  Yen-Cheng Liu

IPC: G06F12/02 ,  G06F13/16

CPC classification number: G06F12/0292 ,  G06F12/0238 ,  G06F13/161 ,  G06F13/1642 ,  G06F13/1668 ,  G06F2212/1021

Abstract: Techniques and mechanisms for identifying a memory access resource which is to be a target of an access request. In an embodiment, a processor comprises route tables which are to provide entries corresponding to different respective memory access resources which are coupled to the processor. The processor further comprises a list of items which each correspond to a different respective range of addresses, wherein the items each include an identifier of a respective route table, and an identifier of a respective index offset. Based on an address of the access request, a decoder circuit of the processor searches the list to identify a corresponding one of the items. In another embodiment, the decoder circuit accesses a route table entry, based on the search, to determine how the access request is to be directed to a particular memory access resource.

公开(公告)号：US20230195616A1

公开(公告)日：2023-06-22

申请号：US17553458

申请日：2021-12-16

Applicant: Intel Corporation

Inventor： Monam Agarwal ,  Anand K. Enamandram ,  Wei Chen ,  Kerry Vander Kamp ,  Robert A. Branch ,  Yen-Cheng Liu

IPC: G06F13/16 ,  G06F12/02

CPC classification number: G06F13/161 ,  G06F12/0238 ,  G06F12/0292 ,  G06F13/1642 ,  G06F13/1668 ,  G06F2212/1021

Abstract: Techniques and mechanisms for identifying a memory access resource which is to be a target of an access request. In an embodiment, a processor comprises route tables which are to provide entries corresponding to different respective memory access resources which are coupled to the processor. The processor further comprises a list of items which each correspond to a different respective range of addresses, wherein the items each include an identifier of a respective route table, and an identifier of a respective index offset. Based on an address of the access request, a decoder circuit of the processor searches the list to identify a corresponding one of the items. In another embodiment, the decoder circuit accesses a route table entry, based on the search, to determine how the access request is to be directed to a particular memory access resource.