公开(公告)号：US20240413031A1

公开(公告)日：2024-12-12

申请号：US18207808

申请日：2023-06-09

Applicant: Intel Corporation

Inventor： Chandru Periasamy ,  Jagat Shakya ,  Joshua Jeremy Cardiel Rivera ,  Jaime A. Sanchez ,  Devesh Srivastava ,  Feras Eid ,  Matthew Zeman ,  Xavier F. Brun ,  Nabankur Deb

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/367 ,  H01L23/373

Abstract: An electronic device and associated methods are disclosed. Electronic devices are shown that include a semiconductor die and a patterned layer connected to a backside of the die. Electronic devices are shown that include a pattern of elements across a patterned layer that varies across the backside of a die. Electronic devices are further shown that include a compliant filler within elements in a patterned layer.

公开(公告)号：US20230317546A1

公开(公告)日：2023-10-05

申请号：US17710670

申请日：2022-03-31

Applicant: Intel Corporation

Inventor： Xavier Brun ,  Nabankur Deb ,  Feras Eid

IPC: H01L23/367 ,  H01L21/78

CPC classification number: H01L23/367 ,  H01L21/78 ,  H01L23/3135

Abstract: Embodiments are directed to a device having an overhang portion. In some embodiments, a main body structure of the device comprises an IC die and an exterior surface of the main body structure comprises the overhang portion. The overhang portion adjoins a sidewall structure of the main body structure of the device, which is substantially perpendicular to a backside of the IC die. In some embodiments, the main body structure further comprises a package mold structure, which comprises the overhang portion.