公开(公告)号：US12080620B2

公开(公告)日：2024-09-03

申请号：US16912432

申请日：2020-06-25

Applicant: Intel Corporation

Inventor： Feras Eid ,  Xavier Brun ,  Paul Diglio ,  Joe Walczyk ,  Sergio Antonio Chan Arguedas

IPC: H01L23/373 ,  B33Y70/00 ,  B33Y80/00

CPC classification number: H01L23/3735 ,  B33Y70/00 ,  B33Y80/00

Abstract: An integrated circuit assembly may be fabricated to include an integrated circuit device having a backside surface and a backside metallization layer on the backside surface of the integrated circuit device, wherein the backside metallization layer comprises a bond layer on the backside surface of the integrated circuit device, a high thermal conductivity layer on the bond layer, and a cap layer on the high thermal conductivity layer. The bond layer may be a layered stack comprising an adhesion promotion layer on the backside of the integrated circuit device and at one least metal layer. The high thermal conductivity layer may be an additively deposited material having a thermal conductivity greater than silicon, such as copper, silver, aluminum, diamond, silicon carbide, boron nitride, aluminum nitride, and combinations thereof.

公开(公告)号：US20240063071A1

公开(公告)日：2024-02-22

申请号：US17891880

申请日：2022-08-19

Applicant: Intel Corporation

Inventor： Jeffery Bielefeld ,  Adel Elsherbini ,  Bhaskar Jyoti Krishnatreya ,  Feras Eid ,  Gauri Auluck ,  Kimin Jun ,  Mohammad Enamul Kabir ,  Nagatoshi Tsunoda ,  Renata Camillo-Castillo ,  Tristan A. Tronic ,  Xavier Brun

IPC: H01L23/31 ,  H01L25/065 ,  H01L23/00 ,  H01L23/367 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00

CPC classification number: H01L23/3128 ,  H01L25/0655 ,  H01L24/08 ,  H01L23/367 ,  H01L23/49827 ,  H01L23/49838 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/56 ,  H01L24/80 ,  H01L25/50 ,  H01L2224/08225 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: Multi-die composite structures including a multi-layered inorganic dielectric gap fill material within a space between adjacent IC dies. A first layer of fill material with an inorganic composition may be deposited over IC dies with a high-rate deposition process, for example to at least partially fill a space between the IC dies. The first layer of fill material may then be partially removed to modify a sidewall slope of the first layer or otherwise reduce an aspect ratio of the space between the IC dies. Another layer of fill material may be deposited over the lower layer of fill material, for example with the same high-rate deposition process. This dep-etch-dep cycle may be repeated any number of times to backfill spaces between IC dies. The multi-layer fill material may then be globally planarized and the IC die package completed and/or assembled into a next-level of integration.

公开(公告)号：US20240113005A1

公开(公告)日：2024-04-04

申请号：US17957751

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Jeremy Ecton ,  Aleksandar Aleksov ,  Hiroki Tanaka ,  Brandon Marin ,  Srinivas Pietambaram ,  Xavier Brun

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L23/13

CPC classification number: H01L23/49833 ,  H01L21/4803 ,  H01L21/481 ,  H01L21/4846 ,  H01L23/13 ,  H01L23/49894 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L24/16 ,  H01L2224/0346 ,  H01L2224/05647 ,  H01L2224/08145 ,  H01L2224/08225 ,  H01L2224/16146 ,  H01L2224/1624 ,  H01L2224/80201 ,  H01L2224/80379 ,  H01L2924/0665

Abstract: Microelectronic integrated circuit package structures include a first substrate coupled to a second substrate by a conductive interconnect structure and a dielectric material adjacent to the conductive interconnect structure. A cavity in a surface of the first substrate is adjacent to the conductive interconnect structure. A portion of the dielectric material is within the cavity.

公开(公告)号：US20240063142A1

公开(公告)日：2024-02-22

申请号：US17891666

申请日：2022-08-19

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Wenhao Li ,  Bhaskar Jyoti Krishnatreya ,  Tushar Talukdar ,  Botao Zhang ,  Yi Shi ,  Haris Khan Niazi ,  Feras Eid ,  Nagatoshi Tsunoda ,  Xavier Brun ,  Mohammad Enamul Kabir ,  Omkar Karhade ,  Shawna Liff ,  Jiraporn Seangatith

IPC: H01L23/00 ,  H01L23/367 ,  H01L23/31 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L23/562 ,  H01L23/367 ,  H01L23/3128 ,  H01L23/49827 ,  H01L23/49838 ,  H01L21/486 ,  H01L21/565 ,  H01L25/0655 ,  H01L25/50

Abstract: Multi-die packages including IC die crack mitigation features. Prior to the bonding of IC dies to a host substrate, the IC dies may be shaped, for example with a corner radius or chamfer. After bonding the shaped IC dies, a fill comprising at least one inorganic material may be deposited over the IC dies, for example to backfill a space between adjacent IC dies. With the benefit of a greater IC die sidewall slope and/or smoother surface topology associated with the shaping process, occurrences of stress cracking within the fill and concomitant damage to the IC dies may be reduced. Prior to depositing a fill, a barrier layer may be deposited over the IC die to prevent cracks that might form in the fill material from propagating into the IC die.

公开(公告)号：US20240063089A1

公开(公告)日：2024-02-22

申请号：US17891738

申请日：2022-08-19

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Wenhao Li ,  Bhaskar Jyoti Krishnatreya ,  Debendra Mallik ,  Krishna Vasanth Valavala ,  Lei Jiang ,  Yoshihiro Tomita ,  Omkar Karhade ,  Haris Khan Niazi ,  Tushar Talukdar ,  Mohammad Enamul Kabir ,  Xavier Brun ,  Feras Eid

IPC: H01L23/46

CPC classification number: H01L23/46 ,  G02B6/4268

Abstract: Microelectronic devices, assemblies, and systems include a multichip composite device having one or more integrated circuit dies bonded to a base die and an inorganic dielectric material adjacent the integrated circuit dies and over the base die. The multichip composite device includes a dummy die, dummy vias, or integrated fluidic cooling channels laterally adjacent the integrated circuit dies to conduct heat from the base die.

公开(公告)号：US20240063147A1

公开(公告)日：2024-02-22

申请号：US17891704

申请日：2022-08-19

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Mohammad Enamul Kabir ,  Johanna Swan ,  Omkar Karhade ,  Kimin Jun ,  Feras Eid ,  Shawna Liff ,  Xavier Brun ,  Bhaskar Jyoti Krishnatreya ,  Tushar Talukdar ,  Haris Khan Niazi

IPC: H01L23/00 ,  H01L25/065 ,  H01L21/56 ,  H01L23/31 ,  H01L23/29

CPC classification number: H01L23/564 ,  H01L24/08 ,  H01L24/24 ,  H01L25/0652 ,  H01L24/19 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/291 ,  H01L2224/08145 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2924/37001 ,  H01L2224/24145 ,  H01L24/73 ,  H01L2224/73259 ,  H01L2224/24225 ,  H01L2224/73209 ,  H01L2224/2499

Abstract: Techniques and mechanisms to mitigate corrosion to via structures of a composite chiplet. In an embodiment, a composite chiplet comprises multiple integrated circuit (IC) components which are each in a different respective one of multiple levels. One or more conductive vias extend through an insulator layer in a first level of the multiple levels. An annular structure of the composite chiplet extends vertically through the insulator layer, and surrounds the one or more conductive vias in the insulator layer. The annular structure mitigates an exposure of the one or more conductive vias to moisture which is in a region of the insulator layer that is not surrounded by the annular structure. In another embodiment, the annular structure further surrounds an IC component which extends in the insulator layer.

公开(公告)号：US20240063076A1

公开(公告)日：2024-02-22

申请号：US17891727

申请日：2022-08-19

Applicant: Intel Corporation

Inventor： Mohammad Enamul Kabir ,  Bhaskar Jyoti Krishnatreya ,  Kimin Jun ,  Adel Elsherbini ,  Tushar Talukdar ,  Feras Eid ,  Debendra Mallik ,  Krishna Vasanth Valavala ,  Xavier Brun

IPC: H01L23/367 ,  H01L23/00 ,  H01L23/373 ,  H01L23/48 ,  H01L25/065

CPC classification number: H01L23/367 ,  H01L24/08 ,  H01L23/3736 ,  H01L23/373 ,  H01L23/3732 ,  H01L23/481 ,  H01L24/32 ,  H01L24/29 ,  H01L25/0657 ,  H01L2224/08145 ,  H01L2224/32225 ,  H01L2224/29147 ,  H01L2224/29124 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29193 ,  H01L2224/29186

Abstract: Microelectronic devices, assemblies, and systems include a multichip composite device having one or more integrated circuit dies bonded to a base die, a conformal thermal heat spreading layer on the top and sidewalls of the integrated circuit dies, and an inorganic dielectric material on a portion of the conformal thermal heat spreading layer, laterally adjacent the integrated circuit dies, and over the base die. The conformal thermal heat spreading layer includes a high thermal conductivity material to provide a thermal pathway for the integrated circuit dies during operation.

公开(公告)号：US20230317549A1

公开(公告)日：2023-10-05

申请号：US17709064

申请日：2022-03-30

Applicant: Intel Corporation

Inventor： Feras Eid ,  Wenhao Li ,  Paul Diglio ,  Xavier Brun ,  Johanna Swan

IPC: H01L23/373 ,  H01L21/48

CPC classification number: H01L23/3733 ,  H01L21/4871

Abstract: A porous mesh structure for use in the thermal management of integrated circuit devices may be formed as a solid matrix with a plurality of pores dispersed therein, wherein the solid matrix may be a plurality of fused matrix material particles and the plurality of pores may comprise between about 10% and 90% of a volume of the porous mesh structure. The porous mesh structure may be formed on an integrated circuit device and/or on a heat dissipation assembly component, and may be incorporated into an immersion cooling assembly, wherein the porous mesh structure may act as a nucleation site for a working fluid in the immersion cooling assembly.

公开(公告)号：US20220165625A1

公开(公告)日：2022-05-26

申请号：US17100449

申请日：2020-11-20

Applicant: Intel Corporation

Inventor： Xavier Brun ,  Timothy Gosselin

IPC: H01L21/84 ,  H01L21/762 ,  H01L21/768

Abstract: An integrated circuit package may be fabricated with a universal dummy device, instead of utilizing a dummy device that matches the bump layer of an electronic substrate of the integrated circuit package. In one embodiment, the universal dummy device may comprise a device substrate having an attachment surface and a metallization layer on the attachment surface, wherein the metallization layer is utilized to form a connection with the electronic substrate of the integrated circuit package. In a specific embodiment, the metallization layer may be a single structure extending across the entire attachment surface. In another embodiment, the metallization layer may be patterned to enable gap control between the universal dummy device and the electronic substrate.

公开(公告)号：US20210249322A1

公开(公告)日：2021-08-12

申请号：US16788186

申请日：2020-02-11

Applicant: INTEL CORPORATION

Inventor： Ziyin Lin ,  Vipul Mehta ,  Wei Li ,  Edvin Cetegen ,  Xavier Brun ,  Yang Guo ,  Soud Choudhury ,  Shan Zhong ,  Christopher Rumer ,  Nai-Yuan Liu ,  Ifeanyi Okafor ,  Hsin-Wei Wang

IPC: H01L23/31 ,  H01L23/367 ,  H01L23/00

Abstract: An integrated circuit assembly may be formed comprising an electronic substrate, a first and second integrated circuit device each having a first surface, a second surface, at least one side extending between the first and second surface, and an edge defined at an intersection of the second surface and the at least one side of each respective integrated circuit device, wherein the first surface of each integrated circuit device is electrically attached to the electronic substrate, an underfill material between the first surface of each integrated circuit device and the electronic substrate, and between the sides of the first and second integrated circuit devices, and at least one barrier structure adjacent at least one of the edge of first integrated circuit device and the edge of the second integrated circuit device, wherein the underfill material abuts the at least one barrier structure.