公开(公告)号：US20230198912A1

公开(公告)日：2023-06-22

申请号：US17553543

申请日：2021-12-16

Applicant: Intel Corporation

Inventor： Niall MCDONNELL ,  Pravin PATHAK ,  Rahul SHAH ,  Declan DOHERTY

IPC: H04L47/34 ,  H04L47/2441 ,  H04L47/27

CPC classification number: H04L47/34 ,  H04L47/2441 ,  H04L47/27 ,  H04L63/18

Abstract: Methods and apparatus to assign and check anti-replay sequence numbers. In one embodiment, a method includes assigning, by circuitry, sequence numbers to packets of traffic flows, wherein a first sequence number is assigned to a first packet based on a determination that the first packet is within a first traffic flow mapped to a first secure channel, and wherein the first sequence number is within a set of sequence numbers allocated to the first secure channel and maintained by the circuitry. The method continues with allocating the packets of traffic flows to be processed among a plurality of processor cores and processing the packets of traffic flows by the plurality of processor cores.

公开(公告)号：US20240121194A1

公开(公告)日：2024-04-11

申请号：US18392028

申请日：2023-12-21

Applicant: Intel Corporation

Inventor： Niall MCDONNELL ,  Ambalavanar ARULAMBALAM ,  Bruce RICHARDSON ,  Te MA

IPC: H04L47/125 ,  H04L47/30 ,  H04L47/625

CPC classification number: H04L47/125 ,  H04L47/30 ,  H04L47/6255

Abstract: Methods, apparatus, and computer programs are disclosed for buffer management in load balancing. In one embodiment, a method is disclosed to comprise providing a set of buffers by a storage of a load balancer to store packets to be distributed by the load balancer, and distributing the packets by the load balancer to a set of cores of a computer processor to be processed by the set of cores. The method further comprises responsive to buffer utilization in the storage over a first threshold, obtaining by circuitry of the load balancer, from top of a memory stack coupled to the storage, additional buffers to store the packets to be distributed and responsive to buffer utilization in the storage below a second threshold, returning by the circuitry of the load balancer, available buffers in the storage to the top of the memory stack.

公开(公告)号：US20220107838A1

公开(公告)日：2022-04-07

申请号：US17644117

申请日：2021-12-14

Applicant: Intel Corporation

Inventor： Niall MCDONNELL ,  Bruce RICHARDSON ,  Rahul SHAH ,  Pravin PATHAK ,  Rashmi SHETTY

IPC: G06F9/48

Abstract: Examples relate to an apparatus, device, method, and computer program for processing a sequence of units of data, and of a computer program comprising such an apparatus or device. The apparatus comprises processing circuitry configured to obtain the sequence of units of data, obtain tokens indicating a readiness of a plurality of worker threads being executed on the processing circuitry, and process sub-sequences of the sequence of units of data by selecting, by a queue management circuitry of the processing circuitry, a worker thread from the plurality of worker threads based on the obtained tokens indicating the readiness, providing, by the queue management circuitry, a lock to a queue associated with the worker thread, the lock being associated with a resource comprising a sub-sequence of the sequence of units of data, obtaining, by the queue management circuitry, the lock from the worker thread after the worker thread has at least partially processed the sub-sequence of units of data stored in the resource, and proceeding with the next sub-sequence after the lock has been obtained.

公开(公告)号：US20160275026A1

公开(公告)日：2016-09-22

申请号：US14663785

申请日：2015-03-20

Applicant: INTEL CORPORATION

Inventor： Niall MCDONNELL ,  Tomasz KANTECKI ,  Ryan CARLSON ,  Michael O'HANLON

IPC: G06F13/28 ,  G06F13/16 ,  G06F12/10 ,  G06F12/08 ,  G06F12/12

Abstract: A weakly ordered doorbell at least reduces the cycle cost of talking to a device. This may manifest as simple performance improvement, but it also allows a reduction in the number of jobs batched into a single doorbell—current DPDK (Data Plane Development Kit) code (for example) batches larger numbers of packets behind a single doorbell to amortize the per-packet doorbell cost. Reducing the number of packets at least provide a better latency profile.

Abstract translation: 一个弱排序的门铃至少减少了与设备通话的周期成本。 这可能表现为简单的性能改进，但它也可以减少分配到单个门铃当前DPDK（数据平面开发套件）代码中的作业数量（例如）批次在单个门铃后面分配更多数量的数据包，以分摊 每包门铃成本。 减少数据包数量至少提供更好的延迟配置文件。