Reducing decode delay at a client device

    公开(公告)号:US12081448B2

    公开(公告)日:2024-09-03

    申请号:US17360126

    申请日:2021-06-28

    申请人: Synamedia Limited

    IPC分类号: H04L47/30 H04L43/16 H04L65/61

    CPC分类号: H04L47/30 H04L43/16 H04L65/61

    摘要: Various implementations disclosed herein include devices, systems, and methods for reducing a decode delay at a client device. In some implementations, a device includes one or more processors and a non-transitory memory. In some implementations, a method includes determining that a client device is being switched from a real-time content presentation mode in which the client device presents real-time content to a buffered content presentation mode in which the client device presents buffered content. In some implementations, the method includes transmitting, to the client device, video frames corresponding to the buffered content at a first transmission rate. In some implementations, the method includes changing the first transmission rate to a second transmission rate based on an indication that a number of bits stored in a buffer of the client device satisfies a decode threshold.

    METHOD AND SYSTEM FOR GRANULAR DYNAMIC QUOTA-BASED CONGESTION MANAGEMENT

    公开(公告)号:US20240259315A1

    公开(公告)日:2024-08-01

    申请号:US18443475

    申请日:2024-02-16

    摘要: A system for facilitating sender-side granular congestion control is provided. During operation, the first and second processes of an application can run on sender and receiver nodes, respectively. A first buffer on the sender node can be allocated to the first process. For the first process, the system can then identify a second buffer at a last-hop switch of the receiver node. The system can determine, based on in-flight packets, the utilization of the second buffer. The system can also determine a fraction of available space in the second buffer for packets from the first buffer based on the utilization. Subsequently, the system can determine whether the fraction of the available space can accommodate the next packet from the first buffer. If the fraction of the available space can accommodate the next packet, the system can allow the first process to send the next packet to the second process.

    Allocation of shared reserve memory
    8.
    发明公开

    公开(公告)号:US20240195754A1

    公开(公告)日:2024-06-13

    申请号:US18581423

    申请日:2024-02-20

    摘要: A device includes ports, a packet processor, and a memory management circuit. The ports communicate packets over a network. The packet processor processes the packets using queues. The memory management circuit maintains a shared buffer in a memory and adaptively allocates memory resources from the shared buffer to the queues, maintains in the memory, in addition to the shared buffer, a shared-reserve memory pool for use by the queues, identifies, among the queues, a queue that requires additional memory resources, the queue having an occupancy that is (i) above a current value of a dynamic threshold, rendering the queue ineligible for additional allocation from the shared buffer, and (ii) no more than a defined margin above the current value of the dynamic threshold, rendering the queue eligible for allocation from the shared-reserve memory pool, and allocates memory resources to the identified queue from the shared-reserve memory pool.

    DEADLOCK PREVENTION OF SWITCH MEMORY OVERFLOW

    公开(公告)号:US20240195742A1

    公开(公告)日:2024-06-13

    申请号:US18063346

    申请日:2022-12-08

    发明人: Andrea Enrici

    IPC分类号: H04L47/12 H04L45/02 H04L47/30

    CPC分类号: H04L47/12 H04L45/02 H04L47/30

    摘要: Example embodiments disclose a method for avoiding deadlock in a network includes generating a finite state machine indicating possible routing decisions of incoming packets for a plurality of switches, analyzing the finite state machine, determining at least one memory overflow state based on the analyzing, generating at least one anti-deadlock rule in response to determining the at least one memory overflow state, and transmitting the at least one anti-deadlock rule to the plurality of switches.