公开(公告)号：US20240265232A1

公开(公告)日：2024-08-08

申请号：US18565972

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Darren Crews ,  Yong Jiang ,  Yuanyuan Li ,  Xu Qian ,  Peiqing Jiang ,  Haiyun Hong

IPC: G06N3/04

CPC classification number: G06N3/04

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed. An example apparatus includes at least one memory, instructions in the apparatus, and processor circuitry to execute the instructions to detect a pattern of an upsampled input submatrix, generate a transformed input submatrix by selecting four elements of the upsampled input submatrix, select a transformed weight submatrix based on the pattern, and convolve the transformed input submatrix and the transformed weight submatrix.

公开(公告)号：US12066946B2

公开(公告)日：2024-08-20

申请号：US17704340

申请日：2022-03-25

Applicant: Intel Corporation

Inventor： Xiaodong Qiu ,  Yong Jiang ,  Changwon Rhee ,  Cui Tang ,  Shuangpeng Zhou ,  Lei Chen ,  Danyu Bi ,  Peiqing Jiang ,  Chengxi Wu

IPC: G06F12/084 ,  G06F9/48

CPC classification number: G06F12/084 ,  G06F9/4818 ,  G06F2212/604

Abstract: Embodiments are generally directed to methods and apparatuses for dynamically changing data priority in a cache. An embodiment of an apparatus comprising: a priority controller to: receive a memory access request to request data; and set a priority flag for the memory access request based on an accumulated access amount of data stored in a memory block to be accessed by the memory access request to dynamically change a priority level of the requested data.

公开(公告)号：US20240370372A1

公开(公告)日：2024-11-07

申请号：US18763009

申请日：2024-07-03

Applicant: Intel Corporation

Inventor： Xiaodong Qiu ,  Yong Jiang ,  Changwon Rhee ,  Cui Tang ,  Shuangpeng Zhou ,  Lei Chen ,  Danyu Bi ,  Peiqing Jiang ,  Chengxi Wu

IPC: G06F12/084 ,  G06F9/48

Abstract: Embodiments are generally directed to methods and apparatuses for dynamically changing data priority in a cache. An embodiment of an apparatus comprising: a priority controller to: receive a memory access request to request data; and set a priority flag for the memory access request based on an accumulated access amount of data stored in a memory block to be accessed by the memory access request to dynamically change a priority level of the requested data.

公开(公告)号：US20220414010A1

公开(公告)日：2022-12-29

申请号：US17704340

申请日：2022-03-25

Applicant: Intel Corporation

Inventor： Xiaodong Qiu ,  Yong Jiang ,  Changwon Rhee ,  Cui Tang ,  Shuangpeng Zhou ,  Lei Chen ,  Danyu Bi ,  Peiqing Jiang ,  Chengxi Wu

IPC: G06F12/084 ,  G06F9/48

Abstract: Embodiments are generally directed to methods and apparatuses for dynamically changing data priority in a cache. An embodiment of an apparatus comprising: a priority controller to: receive a memory access request to request data; and set a priority flag for the memory access request based on an accumulated access amount of data stored in a memory block to be accessed by the memory access request to dynamically change a priority level of the requested data.