公开(公告)号：US20240370372A1

公开(公告)日：2024-11-07

申请号：US18763009

申请日：2024-07-03

Applicant: Intel Corporation

Inventor： Xiaodong Qiu ,  Yong Jiang ,  Changwon Rhee ,  Cui Tang ,  Shuangpeng Zhou ,  Lei Chen ,  Danyu Bi ,  Peiqing Jiang ,  Chengxi Wu

IPC: G06F12/084 ,  G06F9/48

Abstract: Embodiments are generally directed to methods and apparatuses for dynamically changing data priority in a cache. An embodiment of an apparatus comprising: a priority controller to: receive a memory access request to request data; and set a priority flag for the memory access request based on an accumulated access amount of data stored in a memory block to be accessed by the memory access request to dynamically change a priority level of the requested data.

公开(公告)号：US20220414010A1

公开(公告)日：2022-12-29

申请号：US17704340

申请日：2022-03-25

Applicant: Intel Corporation

Inventor： Xiaodong Qiu ,  Yong Jiang ,  Changwon Rhee ,  Cui Tang ,  Shuangpeng Zhou ,  Lei Chen ,  Danyu Bi ,  Peiqing Jiang ,  Chengxi Wu

IPC: G06F12/084 ,  G06F9/48

Abstract: Embodiments are generally directed to methods and apparatuses for dynamically changing data priority in a cache. An embodiment of an apparatus comprising: a priority controller to: receive a memory access request to request data; and set a priority flag for the memory access request based on an accumulated access amount of data stored in a memory block to be accessed by the memory access request to dynamically change a priority level of the requested data.

公开(公告)号：US10789124B2

公开(公告)日：2020-09-29

申请号：US16145983

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Lei Chen ,  Xin Guo ,  Shu-Jen Lee ,  Chu-hsiang Teng ,  Scott Nelson ,  Donia Sebastian

IPC: G06F11/10 ,  G11C16/26 ,  G11C16/34 ,  G11C29/02 ,  G11C29/04

Abstract: Examples described herein can be used to reduce a number of re-read operations and potentially avoid data recovery operations, which can be time consuming. A determination can be made of a read voltage to apply during an operation to cause a read of data stored in a region of a memory device. The region of the memory device can be read using the read voltage. If the region is not successfully read, then an error level indication can be measured and a second read voltage can be determined for a re-read operation. If the re-read operation is not successful, then a second error level indication can be measured for the re-read operation. A third read voltage can be selected based on the change from the error level indication to the second error level indication.

公开(公告)号：US20190180829A1

公开(公告)日：2019-06-13

申请号：US16276695

申请日：2019-02-15

Applicant: Intel Corporation

Inventor： Lei Chen ,  Xin Guo ,  Ali Khakifirooz ,  Aliasgar Madraswala ,  Yogesh B. Wakchaure

IPC: G11C16/34 ,  G11C16/26 ,  G11C7/22 ,  G06F11/07

Abstract: An embodiment of a semiconductor apparatus may include technology to determine an error rate associated with a read request for a persistent storage media, compare the determined error rate against a pre-fail threshold, and adjust a read voltage shift direction for the persistent storage media if the determined error rate exceeds the pre-fail threshold. Other embodiments are disclosed and claimed.

公开(公告)号：US12066946B2

公开(公告)日：2024-08-20

申请号：US17704340

申请日：2022-03-25

Applicant: Intel Corporation

Inventor： Xiaodong Qiu ,  Yong Jiang ,  Changwon Rhee ,  Cui Tang ,  Shuangpeng Zhou ,  Lei Chen ,  Danyu Bi ,  Peiqing Jiang ,  Chengxi Wu

IPC: G06F12/084 ,  G06F9/48

CPC classification number: G06F12/084 ,  G06F9/4818 ,  G06F2212/604

Abstract: Embodiments are generally directed to methods and apparatuses for dynamically changing data priority in a cache. An embodiment of an apparatus comprising: a priority controller to: receive a memory access request to request data; and set a priority flag for the memory access request based on an accumulated access amount of data stored in a memory block to be accessed by the memory access request to dynamically change a priority level of the requested data.

公开(公告)号：US09992483B2

公开(公告)日：2018-06-05

申请号：US14576792

申请日：2014-12-19

Applicant: INTEL CORPORATION

Inventor： Krishna Kaza ,  Vivek Kumar ,  Kabeer R. Manchanda ,  Sreenivasulu Gosangi ,  Jianxu Zheng ,  Lei Chen ,  Wen Wang

IPC: H04N5/247 ,  H04N13/02 ,  G01B11/245

CPC classification number: H04N13/296 ,  G01B11/245 ,  H04N5/2258 ,  H04N13/271

Abstract: An imaging architecture is described for a depth camera mode with mode switching. In one example, an imaging device has a primary camera to capture an image of a scene, a secondary camera to capture an image of the same scene, a third camera to capture an image of a second scene, a processor having a first port coupled to the primary camera to receive images from the primary camera and a second port to receive images, and a multiplexer coupled to the secondary camera and to the third camera to receive the captured images and to alternately couple the secondary camera or the third camera to the second port of the processor.