公开(公告)号：US20220414010A1

公开(公告)日：2022-12-29

申请号：US17704340

申请日：2022-03-25

申请人： Intel Corporation

发明人： Xiaodong Qiu ,  Yong Jiang ,  Changwon Rhee ,  Cui Tang ,  Shuangpeng Zhou ,  Lei Chen ,  Danyu Bi ,  Peiqing Jiang ,  Chengxi Wu

IPC分类号： G06F12/084 ,  G06F9/48

摘要： Embodiments are generally directed to methods and apparatuses for dynamically changing data priority in a cache. An embodiment of an apparatus comprising: a priority controller to: receive a memory access request to request data; and set a priority flag for the memory access request based on an accumulated access amount of data stored in a memory block to be accessed by the memory access request to dynamically change a priority level of the requested data.

公开(公告)号：US12066946B2

公开(公告)日：2024-08-20

申请号：US17704340

申请日：2022-03-25

申请人： Intel Corporation

发明人： Xiaodong Qiu ,  Yong Jiang ,  Changwon Rhee ,  Cui Tang ,  Shuangpeng Zhou ,  Lei Chen ,  Danyu Bi ,  Peiqing Jiang ,  Chengxi Wu

IPC分类号： G06F12/084 ,  G06F9/48

CPC分类号： G06F12/084 ,  G06F9/4818 ,  G06F2212/604

摘要： Embodiments are generally directed to methods and apparatuses for dynamically changing data priority in a cache. An embodiment of an apparatus comprising: a priority controller to: receive a memory access request to request data; and set a priority flag for the memory access request based on an accumulated access amount of data stored in a memory block to be accessed by the memory access request to dynamically change a priority level of the requested data.