公开(公告)号：US11935887B2

公开(公告)日：2024-03-19

申请号：US16368077

申请日：2019-03-28

Applicant: Intel Corporation

Inventor： Ryan Keech ,  Nicholas Minutillo ,  Anand Murthy ,  Aaron Budrevich ,  Peter Wells

IPC: H01L29/66 ,  H01L21/8234 ,  H01L23/00 ,  H01L27/088 ,  H01L29/08 ,  H01L29/167 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L24/09 ,  H01L24/17 ,  H01L29/0847 ,  H01L29/167 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858 ,  H01L2224/0401

Abstract: Integrated circuit structures having source or drain structures with vertical trenches are described. In an example, an integrated circuit structure includes a fin having a lower fin portion and an upper fin portion. A gate stack is over the upper fin portion of the fin, the gate stack having a first side opposite a second side. A first source or drain structure includes an epitaxial structure embedded in the fin at the first side of the gate stack. A second source or drain structure includes an epitaxial structure embedded in the fin at the second side of the gate stack. The epitaxial structures of the first and second source or drain structures have a vertical trench centered therein. The first and second source or drain structures include silicon and a Group V dopant impurity.

公开(公告)号：US12224337B2

公开(公告)日：2025-02-11

申请号：US17132951

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Michael Beumer ,  Robert Ehlert ,  Nicholas Minutillo ,  Michael Robinson ,  Patrick Wallace ,  Peter Wells

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66

Abstract: III-N e-mode high electron mobility transistors (HEMTs) including a dopant diffusion spacer between an impurity-doped III-N material layer and a III-N polarization layer of the HEMT material stack. The spacer may be a substantially undoped III-N material, such as GaN. With the diffusion spacer, P-type impurities within the pGaN are setback from the polarization layer sufficiently to avoid significant levels of P-type impurities from entering the III-N material interface where the 2DEG resides. With the diffusion spacer, clustering of impurities near the 2DEG may be avoided and a III-N e-mode HEMT may achieve higher drive currents.

公开(公告)号：US20220199816A1

公开(公告)日：2022-06-23

申请号：US17132951

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Michael Beumer ,  Robert Ehlert ,  Nicholas Minutillo ,  Michael Robinson ,  Patrick Wallace ,  Peter Wells

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/66 ,  H01L29/205

Abstract: III-N e-mode high electron mobility transistors (HEMTs) including a dopant diffusion spacer between an impurity-doped III-N material layer and a III-N polarization layer of the HEMT material stack. The spacer may be a substantially undoped III-N material, such as GaN. With the diffusion spacer, P-type impurities within the pGaN are setback from the polarization layer sufficiently to avoid significant levels of P-type impurities from entering the III-N material interface where the 2DEG resides. With the diffusion spacer, clustering of impurities near the 2DEG may be avoided and a III-N e-mode HEMT may achieve higher drive currents.