公开(公告)号：US20230197840A1

公开(公告)日：2023-06-22

申请号：US17557827

申请日：2021-12-21

Applicant: Intel Corporation

Inventor： Sanyam Bajaj ,  Michael S. Beumer ,  Robert Ehlert ,  Gregory P. McNerney ,  Nicholas Minutillo ,  Xiaoye Qin ,  Johann C. Rode ,  Atsunori Tanaka ,  Suresh Vishwanath ,  Patrick M. Wallace

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/7785 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/42316 ,  H01L29/66462

Abstract: In one embodiment, a transistor includes a substrate, a buffer layer on the substrate a channel layer on the buffer layer, and one or more polarization layers on the channel layer. The one or more polarization layers include a group III-N material comprising a first group III constituent and a second group III constituent. The transistor further includes a plurality of p-type doped layers on the one or more polarization layers. Each of the plurality of p-type doped layers includes a first p-type dopant and the III-N material, wherein each successive layer of the first p-type doped layers has a lower proportion of the first group III constituent to the second group III constituent relative to a layer below it. The transistor also includes a p-type doped layer on the plurality of p-type doped layers comprising a second p-type dopant and a group III-N material.

公开(公告)号：US12224337B2

公开(公告)日：2025-02-11

申请号：US17132951

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Michael Beumer ,  Robert Ehlert ,  Nicholas Minutillo ,  Michael Robinson ,  Patrick Wallace ,  Peter Wells

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66

Abstract: III-N e-mode high electron mobility transistors (HEMTs) including a dopant diffusion spacer between an impurity-doped III-N material layer and a III-N polarization layer of the HEMT material stack. The spacer may be a substantially undoped III-N material, such as GaN. With the diffusion spacer, P-type impurities within the pGaN are setback from the polarization layer sufficiently to avoid significant levels of P-type impurities from entering the III-N material interface where the 2DEG resides. With the diffusion spacer, clustering of impurities near the 2DEG may be avoided and a III-N e-mode HEMT may achieve higher drive currents.

公开(公告)号：US20250006790A1

公开(公告)日：2025-01-02

申请号：US18345931

申请日：2023-06-30

Applicant: Intel Corporation

Inventor： Anand Murthy ,  Shishir Pandya ,  James Kally ,  Robert Ehlert ,  Tahir Ghani

IPC: H01L29/08 ,  H01L21/02 ,  H01L29/167 ,  H01L29/45

Abstract: In some implementations, a device may include a channel material. In addition, the device may include a contact metal. The device may include a first layer between the channel material and the contact metal, the first layer having antimony and silicon. Moreover, the device may include a second layer between the contact metal and the first layer, the second layer having phosphorus and silicon.

公开(公告)号：US20220199816A1

公开(公告)日：2022-06-23

申请号：US17132951

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Michael Beumer ,  Robert Ehlert ,  Nicholas Minutillo ,  Michael Robinson ,  Patrick Wallace ,  Peter Wells

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/66 ,  H01L29/205

Abstract: III-N e-mode high electron mobility transistors (HEMTs) including a dopant diffusion spacer between an impurity-doped III-N material layer and a III-N polarization layer of the HEMT material stack. The spacer may be a substantially undoped III-N material, such as GaN. With the diffusion spacer, P-type impurities within the pGaN are setback from the polarization layer sufficiently to avoid significant levels of P-type impurities from entering the III-N material interface where the 2DEG resides. With the diffusion spacer, clustering of impurities near the 2DEG may be avoided and a III-N e-mode HEMT may achieve higher drive currents.

公开(公告)号：US11955482B2

公开(公告)日：2024-04-09

申请号：US16876495

申请日：2020-05-18

Applicant: Intel Corporation

Inventor： Robert Ehlert ,  Timothy Jen ,  Alexander Badmaev ,  Shridhar Hegde ,  Sandrine Charue-Bakker

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/167 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L21/823418 ,  H01L21/823431 ,  H01L29/0847 ,  H01L29/167 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/7851

Abstract: Integrated circuit structures having high phosphorous dopant concentrations are described. In an example, an integrated circuit structure includes a fin having a lower fin portion and an upper fin portion. A gate stack is over the upper fin portion of the fin, the gate stack having a first side opposite a second side. A first source or drain structure includes an epitaxial structure embedded in the fin at the first side of the gate stack. A second source or drain structure includes an epitaxial structure embedded in the fin at the second side of the gate stack. Each of the epitaxial structures of the first and second source or drain structures includes silicon and phosphorous, the phosphorous having an atomic concentration in a core region of the silicon greater than an atomic concentration in a peripheral region of the silicon.

公开(公告)号：US20230132548A1

公开(公告)日：2023-05-04

申请号：US17519429

申请日：2021-11-04

Applicant: Intel Corporation

Inventor： Atsunori Tanaka ,  Sanyam Bajaj ,  Michael S. Beumer ,  Robert Ehlert ,  Gregory P. McNerney ,  Nicholas Minutillo ,  Johann C. Rode ,  Suresh Vishwanath ,  Patrick M. Wallace

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/66

Abstract: In one embodiment, a transistor is formed by a process comprising forming a buffer layer on a substrate, the buffer layer comprising a first group III-nitride (III-N) material (e.g., AlGaN), forming a channel layer on the buffer layer, the channel layer comprising a second III-N material (e.g., GaN), forming a polarization layer on the channel layer, the polarization layer comprising a third III-N material (e.g., AlGaN), flowing a p-type dopant precursor compound (e.g., Cp2Mg) after forming the polarization layer, forming a p-type doped layer (e.g., p-GaN) on the polarization layer, the p-type doped layer comprising a p-type dopant (e.g., Mg) and a fourth III-N material (e.g., GaN), forming a source region adjacent one end of the channel layer, and forming a drain region adjacent another end of the channel layer.