公开(公告)号：US11735630B2

公开(公告)日：2023-08-22

申请号：US16238858

申请日：2019-01-03

Applicant: Intel Corporation

Inventor： Cory Bomberger ,  Anand Murthy ,  Anupama Bowonder ,  Aaron Budrevich ,  Tahir Ghani

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/161 ,  H01L29/167 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L29/0847 ,  H01L21/02532 ,  H01L21/02579 ,  H01L29/161 ,  H01L29/167 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7851

Abstract: Embodiments of the disclosure include integrated circuit structures having source or drain dopant diffusion blocking layers. In an example, an integrated circuit structure includes a fin including silicon. A gate structure is over a channel region of the fin, the gate structure having a first side opposite a second side. A first source or drain structure is at the first side of the gate structure. A second source or drain structure is at the second side of the gate structure. The first and second source or drain structures include a first semiconductor layer and a second semiconductor layer. The first semiconductor layer is in contact with the channel region of the fin, and the second semiconductor layer is on the first semiconductor layer. The first semiconductor layer has a greater concentration of germanium than the second semiconductor layer, and the second semiconductor layer includes boron dopant impurity atoms.

公开(公告)号：US11935887B2

公开(公告)日：2024-03-19

申请号：US16368077

申请日：2019-03-28

Applicant: Intel Corporation

Inventor： Ryan Keech ,  Nicholas Minutillo ,  Anand Murthy ,  Aaron Budrevich ,  Peter Wells

IPC: H01L29/66 ,  H01L21/8234 ,  H01L23/00 ,  H01L27/088 ,  H01L29/08 ,  H01L29/167 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L24/09 ,  H01L24/17 ,  H01L29/0847 ,  H01L29/167 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858 ,  H01L2224/0401

Abstract: Integrated circuit structures having source or drain structures with vertical trenches are described. In an example, an integrated circuit structure includes a fin having a lower fin portion and an upper fin portion. A gate stack is over the upper fin portion of the fin, the gate stack having a first side opposite a second side. A first source or drain structure includes an epitaxial structure embedded in the fin at the first side of the gate stack. A second source or drain structure includes an epitaxial structure embedded in the fin at the second side of the gate stack. The epitaxial structures of the first and second source or drain structures have a vertical trench centered therein. The first and second source or drain structures include silicon and a Group V dopant impurity.