公开(公告)号：US20220199816A1

公开(公告)日：2022-06-23

申请号：US17132951

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Michael Beumer ,  Robert Ehlert ,  Nicholas Minutillo ,  Michael Robinson ,  Patrick Wallace ,  Peter Wells

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/66 ,  H01L29/205

Abstract: III-N e-mode high electron mobility transistors (HEMTs) including a dopant diffusion spacer between an impurity-doped III-N material layer and a III-N polarization layer of the HEMT material stack. The spacer may be a substantially undoped III-N material, such as GaN. With the diffusion spacer, P-type impurities within the pGaN are setback from the polarization layer sufficiently to avoid significant levels of P-type impurities from entering the III-N material interface where the 2DEG resides. With the diffusion spacer, clustering of impurities near the 2DEG may be avoided and a III-N e-mode HEMT may achieve higher drive currents.

公开(公告)号：US12224337B2

公开(公告)日：2025-02-11

申请号：US17132951

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Michael Beumer ,  Robert Ehlert ,  Nicholas Minutillo ,  Michael Robinson ,  Patrick Wallace ,  Peter Wells

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66

Abstract: III-N e-mode high electron mobility transistors (HEMTs) including a dopant diffusion spacer between an impurity-doped III-N material layer and a III-N polarization layer of the HEMT material stack. The spacer may be a substantially undoped III-N material, such as GaN. With the diffusion spacer, P-type impurities within the pGaN are setback from the polarization layer sufficiently to avoid significant levels of P-type impurities from entering the III-N material interface where the 2DEG resides. With the diffusion spacer, clustering of impurities near the 2DEG may be avoided and a III-N e-mode HEMT may achieve higher drive currents.

公开(公告)号：US20240204091A1

公开(公告)日：2024-06-20

申请号：US18084438

申请日：2022-12-19

Applicant: Intel Corporation

Inventor： Heli Vora ,  Marko Radosavljevic ,  Pratik Koirala ,  Han Wui Then ,  Michael Beumer ,  Ahmad Zubair ,  Samuel Bader

IPC: H01L29/778 ,  H01L21/285 ,  H01L21/306 ,  H01L29/20 ,  H01L29/47 ,  H01L29/66

CPC classification number: H01L29/7786 ,  H01L21/28581 ,  H01L21/30621 ,  H01L29/2003 ,  H01L29/475 ,  H01L29/66462

Abstract: Devices, transistor structures, systems, and techniques are described herein related to low aluminum concentration aluminum gallium nitride interlayers for group III-nitride enhancement mode transistors. The low aluminum concentration aluminum gallium nitride interlayer includes a lower aluminum concentration than a polarization layer of the transistor, such that the polarization layer induces a two-dimensional electron gas in a semiconductor layer of the transistor. The low aluminum concentration aluminum gallium nitride interlayer may be implemented as an etch stop layer, as a gate liner, or both.