公开(公告)号：US20220201836A1

公开(公告)日：2022-06-23

申请号：US17133234

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Arvind S ,  Raghavendra Rao ,  Geejagaaru Krishnamurthy Sandesh

IPC: H05K1/02 ,  H05K3/46

Abstract: A printed circuit board (PCB), comprising a first layer, the first layer comprising a first dielectric material substantially exclusively. The PCB also comprises a second layer, the second layer comprising the first dielectric material within a first region and a second dielectric material within a second region adjacent to first region. The first dielectric material has a first dielectric constant, a first coefficient of thermal expansion (CTE) and a first glass transition temperature (Tg). The second dielectric material has a second dielectric constant, a second CTE and a second Tg. The first dielectric constant is greater than the second dielectric constant. The first CTE is substantially equal to the second CTE; and the first Tg and the second Tg are greater than 150° C.

公开(公告)号：US20230253814A1

公开(公告)日：2023-08-10

申请号：US17592741

申请日：2022-02-04

Applicant: Intel Corporation

Inventor： Jagadish V. Singh ,  Raghavendra Rao ,  Rohit Parakkal ,  Anoop Parchuru

IPC: H02J7/00 ,  H02M3/155

CPC classification number: H02J7/007182 ,  H02M3/155

Abstract: Systems, apparatuses, and methods may provide for power delivery circuit technology that includes a charger controller coupled to a battery output and an intermediate bus converter coupled to an adapter output, a system power input and the battery output, wherein the intermediate bus converter varies a voltage level of the system power input based on the battery output. In one example, the voltage level of the system power input is one or more of a percentage value or an absolute value greater than a voltage level of the battery output. Additionally, the charger controller may connect the battery output to the system power input in response to a turbo power event.

公开(公告)号：US20230207985A1

公开(公告)日：2023-06-29

申请号：US17561802

申请日：2021-12-24

Applicant: Intel Corporation

Inventor： Jagadish Singh ,  Tarakesava Reddy Koki ,  Naoki Matsumura ,  Ming-Chia Lee ,  Raghavendra Rao

IPC: H01M50/538 ,  H01M50/105 ,  H01M4/583 ,  H01M4/525

CPC classification number: H01M50/538 ,  H01M50/105 ,  H01M4/583 ,  H01M4/525

Abstract: Embodiments of the present disclosure are directed to low-profile battery cells. For example, in some embodiments may include multiple cell tabs coupled to cathode and anode layers that are wound, such that the tabs are offset when jelly rolled. Other embodiments may be described and claimed.

公开(公告)号：US12120811B2

公开(公告)日：2024-10-15

申请号：US17133234

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Arvind S ,  Raghavendra Rao ,  Geejagaaru Krishnamurthy Sandesh

IPC: H05K1/02 ,  H05K3/46 ,  H05K1/03

CPC classification number: H05K1/024 ,  H05K1/0231 ,  H05K1/0243 ,  H05K3/4673 ,  H05K3/4688 ,  H05K1/0306 ,  H05K1/036 ,  H05K1/0366 ,  H05K2201/0187

Abstract: A printed circuit board (PCB), comprising a first layer, the first layer comprising a first dielectric material substantially exclusively. The PCB also comprises a second layer, the second layer comprising the first dielectric material within a first region and a second dielectric material within a second region adjacent to first region. The first dielectric material has a first dielectric constant, a first coefficient of thermal expansion (CTE) and a first glass transition temperature (Tg). The second dielectric material has a second dielectric constant, a second CTE and a second Tg. The first dielectric constant is greater than the second dielectric constant. The first CTE is substantially equal to the second CTE; and the first Tg and the second Tg are greater than 150° C.

公开(公告)号：US20240019918A1

公开(公告)日：2024-01-18

申请号：US18472833

申请日：2023-09-22

Applicant: Intel Corporation

Inventor： Ravi Verma ,  Saunak Bhalsod ,  Venkataramani Gopalakrishnan ,  Archana Rao ,  Raghavendra Rao ,  Tomer Savariego ,  Chuen Ming Tan ,  Manjunatha V

IPC: G06F1/26

CPC classification number: G06F1/26

Abstract: A power delivery architecture is described that improves system voltage conversion and operational efficiency. The power delivery architecture performs monitoring of various system conditions such as a current power state, a current power policy setting, workload conditions, component temperatures, a state of charge of a battery, etc. The power delivery architecture may adjust the power profile provided by a power delivery source, which may result in an adjustment to the VBUS voltage and/or current when a USB-based power delivery architecture is implemented. The power delivery architecture may also adjust a mode of operation of an onboard battery charger.