公开(公告)号：US12106815B2

公开(公告)日：2024-10-01

申请号：US17109376

申请日：2020-12-02

Applicant: Intel Corporation

Inventor： Ravi Motwani ,  Pranav Kalavade ,  Rohit Shenoy ,  Rifat Ferdous

IPC: G11C16/04 ,  G06F12/0882 ,  G11C29/14 ,  G11C29/42 ,  G11C29/44

CPC classification number: G11C29/42 ,  G06F12/0882 ,  G11C29/14 ,  G11C29/44

Abstract: Systems, apparatuses and methods may provide for technology that programs a first plurality of error correction codewords to a first set of pages in a block of non-volatile memory, wherein the first plurality of error correction codewords are programmed at a first density. The technology may also program a second plurality of error correction codewords to a second set of pages in the block, wherein the second plurality of error correction codewords are programmed at a second density. The first density and the second density are different from one another.

公开(公告)号：US20210082535A1

公开(公告)日：2021-03-18

申请号：US17109376

申请日：2020-12-02

Applicant: Intel Corporation

Inventor： Ravi Motwani ,  Pranav Kalavade ,  Rohit Shenoy ,  Rifat Ferdous

IPC: G11C29/42 ,  G11C29/44 ,  G11C29/14 ,  G06F12/0882

Abstract: Systems, apparatuses and methods may provide for technology that programs a first plurality of error correction codewords to a first set of pages in a block of non-volatile memory, wherein the first plurality of error correction codewords are programmed at a first density. The technology may also program a second plurality of error correction codewords to a second set of pages in the block, wherein the second plurality of error correction codewords are programmed at a second density. In one example, the first density and the second density are different from one another.