公开(公告)号：US20230044991A1

公开(公告)日：2023-02-09

申请号：US17393877

申请日：2021-08-04

Applicant: Intel Corporation

Inventor： Shantanu Rajwade ,  Kartik Ganapathi ,  Rohit Shenoy ,  Kristopher Gaewsky ,  MarkAnthony Golez ,  Vivek Angoth ,  Pranav Kalavade ,  Sarvesh Gangadhar

IPC: G06F3/06

Abstract: Systems, apparatuses and methods may provide for technology that detects a request to program a NAND memory containing a plurality of dies and programs the NAND memory on a stripe-by-stripe basis, wherein each stripe spans the plurality of dies and includes multiple types of pages. The multiple types of pages may reduce program time variability across the stripes and reduce the error susceptibility of the NAND memory.

公开(公告)号：US20210240388A1

公开(公告)日：2021-08-05

申请号：US16779472

申请日：2020-01-31

Applicant: Intel Corporation

Inventor： Arash Hazeghi ,  Pranav Kalavade ,  Rohit Shenoy ,  Krishna Parat

IPC: G06F3/06 ,  G05B19/406

Abstract: An apparatus and/or system is described including a memory device or a controller for the memory device to perform heating of the memory device. In embodiments, a controller is to receive a temperature of the memory device and determine that the temperature is below a threshold temperature. In embodiments, the controller activates a heater for one or more memory die to assist the memory device in moving the temperature towards the threshold temperature, to assist the memory device when reading data. In embodiments, the heater comprises a plurality of conductive channels included in the one or more memory die or other on-board heater. Other embodiments are disclosed and claimed.

公开(公告)号：US20240354209A1

公开(公告)日：2024-10-24

申请号：US18762492

申请日：2024-07-02

Applicant: Intel Corporation

Inventor： Naveen Vittal Prabhu ,  Aliasgar Madraswala ,  Rohit Shenoy ,  Shankar Natarajan ,  Arun S. Athreya

IPC: G06F11/20 ,  G06F1/30 ,  G06F11/16 ,  G11C29/00

CPC classification number: G06F11/2094 ,  G06F1/30 ,  G06F11/1666 ,  G11C29/76 ,  G06F2201/85

Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to control access to a persistent storage media based on a block and sub-block access structure, store a data structure in the persistent storage media to track read fails at a sub-block granularity for a word-line for every block, and update the data structure in response to a read fail on a block to indicate a failed sub-block that corresponds to the read fail for a word-line for the block. Other embodiments are disclosed and claimed.

公开(公告)号：US12099420B2

公开(公告)日：2024-09-24

申请号：US17133834

申请日：2020-12-24

Applicant: Intel Corporation

Inventor： Naveen Vittal Prabhu ,  Aliasgar Madraswala ,  Rohit Shenoy ,  Shankar Natarajan ,  Arun S. Athreya

IPC: G06F11/00 ,  G06F1/30 ,  G06F11/16 ,  G06F11/20 ,  G11C29/00

CPC classification number: G06F11/2094 ,  G06F1/30 ,  G06F11/1666 ,  G11C29/76 ,  G06F2201/85

Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to control access to a persistent storage media based on a block and sub-block access structure, store a data structure in the persistent storage media to track read fails at a sub-block granularity for a word-line for every block, and update the data structure in response to a read fail on a block to indicate a failed sub-block that corresponds to the read fail for a word-line for the block. Other embodiments are disclosed and claimed.

公开(公告)号：US20210141703A1

公开(公告)日：2021-05-13

申请号：US17133834

申请日：2020-12-24

Applicant: Intel Corporation

Inventor： Naveen Vittal Prabhu ,  Aliasgar Madraswala ,  Rohit Shenoy ,  Shankar Natarajan ,  Arun S. Athreya

IPC: G06F11/20 ,  G06F1/30 ,  G06F16/22

Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to control access to a persistent storage media based on a block and sub-block access structure, store a data structure in the persistent storage media to track read fails at a sub-block granularity for a word-line for every block, and update the data structure in response to a read fail on a block to indicate a failed sub-block that corresponds to the read fail for a word-line for the block. Other embodiments are disclosed and claimed.

公开(公告)号：US12106815B2

公开(公告)日：2024-10-01

申请号：US17109376

申请日：2020-12-02

Applicant: Intel Corporation

Inventor： Ravi Motwani ,  Pranav Kalavade ,  Rohit Shenoy ,  Rifat Ferdous

IPC: G11C16/04 ,  G06F12/0882 ,  G11C29/14 ,  G11C29/42 ,  G11C29/44

CPC classification number: G11C29/42 ,  G06F12/0882 ,  G11C29/14 ,  G11C29/44

Abstract: Systems, apparatuses and methods may provide for technology that programs a first plurality of error correction codewords to a first set of pages in a block of non-volatile memory, wherein the first plurality of error correction codewords are programmed at a first density. The technology may also program a second plurality of error correction codewords to a second set of pages in the block, wherein the second plurality of error correction codewords are programmed at a second density. The first density and the second density are different from one another.

公开(公告)号：US11625191B2

公开(公告)日：2023-04-11

申请号：US16779472

申请日：2020-01-31

Applicant: Intel Corporation

Inventor： Arash Hazeghi ,  Pranav Kalavade ,  Rohit Shenoy ,  Krishna Parat

IPC: G06F3/06 ,  G05B19/406

Abstract: An apparatus and/or system is described including a memory device or a controller for the memory device to perform heating of the memory device. In embodiments, a controller is to receive a temperature of the memory device and determine that the temperature is below a threshold temperature. In embodiments, the controller activates a heater for one or more memory die to assist the memory device in moving the temperature towards the threshold temperature, to assist the memory device when reading data. In embodiments, the heater comprises a plurality of conductive channels included in the one or more memory die or other on-board heater. Other embodiments are disclosed and claimed.

公开(公告)号：US20210082535A1

公开(公告)日：2021-03-18

申请号：US17109376

申请日：2020-12-02

Applicant: Intel Corporation

Inventor： Ravi Motwani ,  Pranav Kalavade ,  Rohit Shenoy ,  Rifat Ferdous

IPC: G11C29/42 ,  G11C29/44 ,  G11C29/14 ,  G06F12/0882

Abstract: Systems, apparatuses and methods may provide for technology that programs a first plurality of error correction codewords to a first set of pages in a block of non-volatile memory, wherein the first plurality of error correction codewords are programmed at a first density. The technology may also program a second plurality of error correction codewords to a second set of pages in the block, wherein the second plurality of error correction codewords are programmed at a second density. In one example, the first density and the second density are different from one another.

公开(公告)号：US20190043567A1

公开(公告)日：2019-02-07

申请号：US16115372

申请日：2018-08-28

Applicant: Intel Corporation

Inventor： Ali Khakifirooz ,  Shantanu Rajwade ,  Rohit Shenoy ,  Aliasgar Madraswala ,  Pranav Kalavade

IPC: G11C11/56 ,  G11C16/26 ,  H01L23/00 ,  G06F3/06

Abstract: An apparatus and/or system is described including a memory device or a controller for a memory device to perform an adjustment of a read operation time for data stored in the memory device. In embodiments, the apparatus may receive a request for data stored in the memory device and a read operation time adjustment module operable by the controller may acquire a first operation temperature of the memory device, obtained at a time of programming of the data stored in the memory device. The apparatus may acquire a second operation temperature of the memory device, obtained after the request for the data stored in the memory device is received. Based at least partially on the first operation temperature and the second operation temperature, the apparatus may adjust the read operation time to read the data. Other embodiments are disclosed and claimed.