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    SOFT READ FOR NVM THAT IS SUBJECT TO DESTRUCTIVE READS
    1.
    发明申请
    SOFT READ FOR NVM THAT IS SUBJECT TO DESTRUCTIVE READS 有权

    公开(公告)号：US20220179582A1

    公开(公告)日：2022-06-09

    申请号：US17678865

    申请日：2022-02-23

    Applicant: Intel Corporation

    Inventor： Zion Kwok ,  Santhosh Vanaparthy ,  Ravi Motwani ,  Poovaiah Manavattira Palangappa

    IPC: G06F3/06

    Abstract: An embodiment of an apparatus may comprise a controller coupled to one or more substrates and including circuitry to control access to NVM with a destructive read characteristic, perform a first read of a codeword from the NVM at a first reference voltage of a low confidence zone, perform a second read of the codeword from the NVM at a second reference voltage of the low confidence zone, and assign a lower confidence value to bits of the codeword that have a different value for the first read of the codeword and the second read of the codeword as compared to a confidence value assigned to bits of the codeword that have a same value for the first read of the codeword and the second read of the codeword. Other embodiments are disclosed and claimed.

    DEVICE, SYSTEM AND METHOD FOR DETERMINING BIT RELIABILITY INFORMATION
    4.
    发明申请
    DEVICE, SYSTEM AND METHOD FOR DETERMINING BIT RELIABILITY INFORMATION 审中-公开

    公开(公告)号：US20190260394A1

    公开(公告)日：2019-08-22

    申请号：US16398003

    申请日：2019-04-29

    Applicant: Intel Corporation

    Inventor： Ravi Motwani ,  Poovaiah Palangappa ,  Santhosh Vanaparthy

    IPC: H03M13/15 ,  H03M13/37 ,  H03M13/39 ,  H03M13/00 ,  G06F11/07 ,  G06F11/10

    Abstract: Techniques and mechanisms for determining information which is to be used for performing bit error correction. In an embodiment, bit reliability information is calculated based on a first likelihood function, and also on data signals which each indicate a respective bit of a codeword. Values of the bit reliability information each indicate, for a respective bit of the codeword, a confidence that the bit is at a particular logic state. A syndrome vector is calculated based on the bit reliability information, and one of the first likelihood function or a second likelihood function is selected based on one or more bit errors which are indicated by the syndrome vector. The selected one of the first likelihood function or the second likelihood function is used to correct bit errors of the codeword. In another embodiment, the first likelihood function is a default likelihood function to be used for initial syndrome vector calculations.

    Distribution of a codeword across individual storage units to reduce the bit error rate
    5.
    发明授权
    Distribution of a codeword across individual storage units to reduce the bit error rate 有权

    公开(公告)号：US10908996B2

    公开(公告)日：2021-02-02

    申请号：US16282725

    申请日：2019-02-22

    Applicant: Intel Corporation

    Inventor： Ravi Motwani

    IPC: G06F11/10 ,  H03M13/39 ,  H03M13/11 ,  H03M13/37

    Abstract: Embodiments are directed towards apparatuses, methods, and systems for a codeword distribution manager to divide a codeword into portions to be written to individual storage units and read from the corresponding different individual storage units to reduce a raw bit error rate (RBER) related to storage of the codeword. In embodiments, the codeword distribution manager is included in a memory controller and the plurality of individual storage units are coupled to the memory controller and include individual memory die or individual pages of a memory die. In embodiments, the codeword is a single codeword and includes encoded data and an error correction code. In some embodiments, the codeword includes a low density parity data check code (LDPC). Additional embodiments may be described and claimed.

    Adjustable error protection for stored data
    6.
    发明授权
    Adjustable error protection for stored data 有权

    公开(公告)号：US10033411B2

    公开(公告)日：2018-07-24

    申请号：US14947801

    申请日：2015-11-20

    Applicant: Intel Corporation

    Inventor： Ravi Motwani

    IPC: G06F3/06 ,  G06F11/10 ,  H03M13/25 ,  H03M13/00 ,  H03M13/35

    Abstract: An apparatus is described that includes a semiconductor chip having memory controller logic circuitry. The memory controller logic circuitry has compression circuitry to compress a cache line data structure to be written into a system memory. The memory controller logic circuitry has adjustable length ECC information generation circuitry to generate an amount of ECC information for the cache line data structure based on an amount of compression applied to the cache line data structure by the compression circuitry. The memory controller logic having circuitry to implement a write process sequence for the cache line data structure that is specific for the cache line data structure's amount of compression and/or amount of ECC information and to implement a different write process sequence that is specific for another cache line data structure having a different amount of compression and/or ECC information as the cache line data structure.

    SOFT READ OPERATIONS WITH PROGRESSIVE DATA OUTPUT
    9.
    发明申请
    SOFT READ OPERATIONS WITH PROGRESSIVE DATA OUTPUT 有权

    公开(公告)号：US20210294698A1

    公开(公告)日：2021-09-23

    申请号：US17342993

    申请日：2021-06-09

    Applicant: Intel Corporation

    Inventor： Ali Khakifirooz ,  George Kalwitz ,  Anand Ramalingam ,  Ravi Motwani ,  Renjie Chen

    IPC: G06F11/10 ,  H03M13/45 ,  G11C11/56 ,  G11C16/04 ,  G11C16/26

    Abstract: Systems, apparatuses and methods may provide for memory controller technology including first logic to trigger, via an initial request, a hard-read and a soft-read, wherein the hard-read is to generate hard-bit information and the soft-read is to generate first soft-bit information and second soft-bit information, conduct a first error correction on the hard-bit information, and issue a subsequent request for at least the second soft-bit information if the first error correction is unsuccessful. Additionally, memory device technology may include a plurality of memory cells and second logic to conduct the hard-read and the soft-read from a memory cell in the plurality of memory cells in response to the initial request, send the hard-bit information to the controller, and withhold at least the second soft-bit information from the controller until the subsequent request is received.

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