公开(公告)号：US20240160568A1

公开(公告)日：2024-05-16

申请号：US17987773

申请日：2022-11-15

Applicant: Intel Corporation

Inventor： Kapil SOOD ,  Lokpraveen MOSUR ,  Aneesh AGGARWAL ,  Niall D. MCDONNELL ,  Chitra NATARAJAN ,  Ritu GUPTA ,  Edwin VERPLANKE ,  George Leonard TKACHUK

IPC: G06F12/0802

CPC classification number: G06F12/0802 ,  G06F2212/60

Abstract: Examples include techniques associated with data movement to a cache in a disaggregated die system. Examples include circuitry at a first die receiving and granting requests to move data to a first cache resident on the first die or to a second cache resident on a second die that also includes a core of a processor. The granting of the request based, at least in part, on a traffic source type associated with a source of the request.

公开(公告)号：US20230101512A1

公开(公告)日：2023-03-30

申请号：US17485372

申请日：2021-09-25

Applicant: Intel Corporation

Inventor： Christopher HUGHES ,  Zhe WANG ,  Dan BAUM ,  Alexander HEINECKE ,  Evangelos GEORGANAS ,  Lingxiang XIANG ,  Joseph NUZMAN ,  Ritu GUPTA

IPC: G06F9/30 ,  G06F12/0862 ,  G06F12/0811

Abstract: Techniques for shared data prefetch are described. An exemplary instruction for shared data prefetch includes at least one field for an opcode, at least one field for a source operand to provide a memory address at least a byte of data, wherein the opcode is to indicate that circuitry is to fetch of a line of data from memory at the provided address that contains the byte specified with the source operand and store that byte in at least a cache local to a requester, wherein the byte of data is to be stored in a shared state.

公开(公告)号：US20230091974A1

公开(公告)日：2023-03-23

申请号：US17482897

申请日：2021-09-23

Applicant: Intel Corporation

Inventor： Ritu GUPTA ,  Stephen R. VAN DOREN

IPC: G06F12/06 ,  G06F12/0842

Abstract: Examples include techniques associated with mapping system memory physical addresses to proximity domains. Examples include mapping system memory physical addresses for a memory coupled with a multi-die system to proximity domains that include cores of a multi-core processor and the associated level 3 (L3) cache for use by each core included in a respective proximity domain. The mapping is to facilitate cache line ownership of a cache line in an L3 cache by an input/output device or agent located on a separate die from the multi-core processor.