公开(公告)号：US10515032B2

公开(公告)日：2019-12-24

申请号：US16099958

申请日：2016-07-01

Applicant: Intel Corporation

Inventor： Zhiming Li ,  Xingping Ruan ,  Xiao Hu ,  Terrence Trausch ,  Robert Pebly ,  Xiang Zhou ,  Jie Yan

IPC: G06F13/20 ,  G06F13/14 ,  G06F13/40 ,  G06F13/42

Abstract: A system includes a host processor (105) and a peripheral device (708). The host processor (105) is coupled to the peripheral device (708) by a Peripheral Component Interconnect Express (PCIe) compliant link. The peripheral device (708) can include logic circuitry to identify, based on an application using the device and the host processor (105), a read to write ratio utilized by the application; and provide the read to write ratio to the host processor (105). The host processor (105) comprising logic circuitry to send a command signal to a device in communication with the hardware processor across a peripheral component interconnect express (PCIe) compliant link, the command signal indicating a transmission (TX) lane to receive (RX) lane ratio, the TX lane to RX lane ratio corresponding to the read to write ratio identified by the peripheral device (708); and receive an indication that the device is capable of supporting asymmetric TX and RX ratios.

公开(公告)号：US20190138470A1

公开(公告)日：2019-05-09

申请号：US16099958

申请日：2016-07-01

Applicant: Intel Corporation

Inventor： Zhiming Li ,  Xingping Ruan ,  Xiao Hu ,  Terrence Trausch ,  Robert Pebly ,  Xiang Zhou ,  Jie Yan

IPC: G06F13/20 ,  G06F13/42

CPC classification number: G06F13/20 ,  G06F13/14 ,  G06F13/4022 ,  G06F13/4282 ,  G06F2213/0026

Abstract: A system includes a host processor (105) and a peripheral device (708). The host processor (105) is coupled to the peripheral device (708) by a Peripheral Component Interconnect Express (PCIe) compliant link. The peripheral device (708) can include logic circuitry to identify, based on an application using the device and the host processor (105), a read to write ratio utilized by the application; and provide the read to write ratio to the host processor (105). The host processor (105) comprising logic circuitry to send a command signal to a device in communication with the hardware processor across a peripheral component interconnect express compliant link, the command signal indicating a transmission (TX) lane to receive (RX) lane ratio, the TX lane to RX lane ratio corresponding to the read to write ratio identified by the peripheral device (708); and receive an indication that the device is capable of supporting asymmetric TX and RX ratios.