公开(公告)号：US20170019088A1

公开(公告)日：2017-01-19

申请号：US15194672

申请日：2016-06-28

Applicant: Intel Corporation

Inventor： Fanzhong Wu ,  Zhigang Li ,  Jie Yan

IPC: H03K3/01

CPC classification number: H03K7/08

Abstract: Provided is a pulse density modulation value converter, comprising: a pulse density modulation reference point storage for storing a plurality of pulse density modulation reference points, each pulse density modulation reference point comprising a linear pulse density modulation value, an actual pulse density modulation value and/or an integral non-linear error value, wherein the integral non-linear error value is the difference between the actual pulse density modulation value and the linear pulse density modulation value; and a pulse density modulation value calculator for receiving a linear pulse density modulation value, searching the pulse density modulation reference point storage for a pair of pulse density modulation reference points closest to the linear pulse density modulation value, obtaining an actual pulse density modulation value corresponding to the linear pulse density modulation value through linear interpolation on the basis of the pair of pulse density modulation reference points, and outputting the actual pulse density modulation value.

Abstract translation: 提供一种脉冲密度调制值转换器，包括：脉冲密度调制参考点存储器，用于存储多个脉冲密度调制参考点，每个脉冲密度调制参考点包括线性脉冲密度调制值，实际脉冲密度调制值和 /或积分非线性误差值，其中积分非线性误差值是实际脉冲密度调制值和线性脉冲密度调制值之间的差; 以及脉冲密度调制值计算器，用于接收线性脉冲密度调制值，在脉冲密度调制参考点存储中搜索最接近于线性脉冲密度调制值的一对脉冲密度调制参考点，获得相应的实际脉冲密度调制值 通过基于一对脉冲密度调制参考点的线性插值来输出线性脉冲密度调制值，并输出实际的脉冲密度调制值。

公开(公告)号：USD867460S1

公开(公告)日：2019-11-19

申请号：US29641867

申请日：2018-03-26

Applicant: Intel Corporation

Designer： Jie Yan ,  La Hung Richard Shih

公开(公告)号：US20240251522A1

公开(公告)日：2024-07-25

申请号：US18587499

申请日：2024-02-26

Applicant: Intel Corporation

Inventor： Yanbing Sun ,  Chao Sun ,  Jie Yan ,  Xiaoguo Liang ,  Lihui Wu

IPC: H05K7/20

CPC classification number: H05K7/20154 ,  H05K7/20209 ,  H05K7/209 ,  H05K7/20927

Abstract: The present disclosure is directed to systems and methods of improving the thermal performance of processor-based devices. Such thermal performance improvement may include a rotatable mount; a first heat sink including a first surface and a second surface, the first surface of the first heat sink to be thermally coupled to a semiconductor device on a substrate, the second surface of the first heat sink thermally coupled to the rotatable mount; and a second heat sink including a third surface, the third surface of the second heat sink coupled to the rotatable mount, the second heat sink structured to rotate relative to the first heat sink when a portion of the rotatable mount rotates between a first position and a second position.

公开(公告)号：US10515032B2

公开(公告)日：2019-12-24

申请号：US16099958

申请日：2016-07-01

Applicant: Intel Corporation

Inventor： Zhiming Li ,  Xingping Ruan ,  Xiao Hu ,  Terrence Trausch ,  Robert Pebly ,  Xiang Zhou ,  Jie Yan

IPC: G06F13/20 ,  G06F13/14 ,  G06F13/40 ,  G06F13/42

Abstract: A system includes a host processor (105) and a peripheral device (708). The host processor (105) is coupled to the peripheral device (708) by a Peripheral Component Interconnect Express (PCIe) compliant link. The peripheral device (708) can include logic circuitry to identify, based on an application using the device and the host processor (105), a read to write ratio utilized by the application; and provide the read to write ratio to the host processor (105). The host processor (105) comprising logic circuitry to send a command signal to a device in communication with the hardware processor across a peripheral component interconnect express (PCIe) compliant link, the command signal indicating a transmission (TX) lane to receive (RX) lane ratio, the TX lane to RX lane ratio corresponding to the read to write ratio identified by the peripheral device (708); and receive an indication that the device is capable of supporting asymmetric TX and RX ratios.

公开(公告)号：US10374590B2

公开(公告)日：2019-08-06

申请号：US15194672

申请日：2016-06-28

Applicant: Intel Corporation

Inventor： Fanzhong Wu ,  Zhigang Li ,  Jie Yan

IPC: H03K7/08

Abstract: Provided is a pulse density modulation value converter, comprising: a pulse density modulation reference point storage for storing a plurality of pulse density modulation reference points, each pulse density modulation reference point comprising a linear pulse density modulation value, an actual pulse density modulation value and/or an integral non-linear error value, wherein the integral non-linear error value is the difference between the actual pulse density modulation value and the linear pulse density modulation value; and a pulse density modulation value calculator for receiving a linear pulse density modulation value, searching the pulse density modulation reference point storage for a pair of pulse density modulation reference points closest to the linear pulse density modulation value, obtaining an actual pulse density modulation value corresponding to the linear pulse density modulation value through linear interpolation on the basis of the pair of pulse density modulation reference points, and outputting the actual pulse density modulation value.

公开(公告)号：US20190138470A1

公开(公告)日：2019-05-09

申请号：US16099958

申请日：2016-07-01

Applicant: Intel Corporation

Inventor： Zhiming Li ,  Xingping Ruan ,  Xiao Hu ,  Terrence Trausch ,  Robert Pebly ,  Xiang Zhou ,  Jie Yan

IPC: G06F13/20 ,  G06F13/42

CPC classification number: G06F13/20 ,  G06F13/14 ,  G06F13/4022 ,  G06F13/4282 ,  G06F2213/0026

Abstract: A system includes a host processor (105) and a peripheral device (708). The host processor (105) is coupled to the peripheral device (708) by a Peripheral Component Interconnect Express (PCIe) compliant link. The peripheral device (708) can include logic circuitry to identify, based on an application using the device and the host processor (105), a read to write ratio utilized by the application; and provide the read to write ratio to the host processor (105). The host processor (105) comprising logic circuitry to send a command signal to a device in communication with the hardware processor across a peripheral component interconnect express compliant link, the command signal indicating a transmission (TX) lane to receive (RX) lane ratio, the TX lane to RX lane ratio corresponding to the read to write ratio identified by the peripheral device (708); and receive an indication that the device is capable of supporting asymmetric TX and RX ratios.