公开(公告)号：US20240265487A1

公开(公告)日：2024-08-08

申请号：US18433823

申请日：2024-02-06

Applicant: Intel Corporation

Inventor： Saikat MANDAL ,  Prasoonkumar SURTI ,  Sven WOOP

IPC: G06T1/20 ,  G06F7/02 ,  G06F7/24 ,  G06F7/505 ,  G06F9/38 ,  G06T15/00 ,  G06T15/08 ,  G06T17/10

CPC classification number: G06T1/20 ,  G06F7/02 ,  G06F7/24 ,  G06F7/505 ,  G06F9/3885 ,  G06T15/005 ,  G06T15/08 ,  G06T17/10

Abstract: Apparatus and method for stable and short latency sorting. For example, one embodiment of a processor comprises: an input circuit to receive a set of N input values to be sorted into a sorted order; comparison circuitry to compare each input value with all other input values in parallel to generate at least N*(N−1)/2 comparison result values; matrix generation circuitry and/or logic to generate a result matrix having a row associated with each input value, a plurality of bits in each row comprising comparison result values indicating results of comparisons with other input values, wherein a first region of the result matrix is to store a first set of bits comprising the N*(N−1)/2 comparison result values and a second region of the result matrix, opposite the first region, is to store a second set of bits comprising an inverse of the N*(N−1)/2 comparison result values; a parallel adder circuit to perform parallel additions of the bits in each row to generate N unique result values; and sorting circuitry to index into the N unique result values to return the sorted order.

公开(公告)号：US20210295463A1

公开(公告)日：2021-09-23

申请号：US16823741

申请日：2020-03-19

Applicant: Intel Corporation

Inventor： Saikat MANDAL ,  Prasoonkumar SURTI ,  Sven WOOP

IPC: G06T1/20 ,  G06T15/00 ,  G06T17/10 ,  G06T15/08 ,  G06F7/24 ,  G06F7/02 ,  G06F7/505 ,  G06F9/38

Abstract: Apparatus and method for stable and short latency sorting. For example, one embodiment of a processor comprises: an input circuit to receive a set of N input values to be sorted into a sorted order; comparison circuitry to compare each input value with all other input values in parallel to generate at least N*(N−1)/2 comparison result values; matrix generation circuitry and/or logic to generate a result matrix having a row associated with each input value, a plurality of bits in each row comprising comparison result values indicating results of comparisons with other input values, wherein a first region of the result matrix is to store a first set of bits comprising the N*(N−1)/2 comparison result values and a second region of the result matrix, opposite the first region, is to store a second set of bits comprising an inverse of the N*(N−1)/2 comparison result values; a parallel adder circuit to perform parallel additions of the bits in each row to generate N unique result values; and sorting circuitry to index into the N unique result values to return the sorted order.