-
公开(公告)号：US20240282053A1
公开(公告)日：2024-08-22
申请号：US18587800
申请日：2024-02-26
申请人： Intel Corporation
发明人： Karthik VAIDYANATHAN , Carsten BENTHIN , Sven WOOP
CPC分类号： G06T17/10 , G06F7/24 , G06T1/20 , G06T15/005 , G06T15/06 , G06T15/08 , G06T17/205
摘要： Apparatus and method for box-box testing. For example, one embodiment of a processor comprises: a bounding volume hierarchy (BVH) generator to construct a BVH comprising a plurality of hierarchically arranged BVH nodes; traversal circuitry to traverse query boxes through the BVH, the traversal circuitry to read a BVH node from a top of a BVH node stack and to read a query box from a local storage or memory, the traversal circuitry further comprising: box-box testing circuitry and/or logic to compare maximum and minimum X, Y, and Z coordinates of the BVH node and the query box and to generate an overlap indication if overlap is detected for each of the X, Y, and Z dimensions; distance determination circuitry and/or logic to generate a distance value representing an extent of overlap between the BVH node and the query box; and sorting circuitry and/or logic to sort the BVH node within a set of one or more additional BVH nodes based on the distance value.
-
公开(公告)号：US20220262063A1
公开(公告)日：2022-08-18
申请号：US17677109
申请日：2022-02-22
申请人： INTEL CORPORATION
摘要： Apparatus and method for grouping rays based on quantized ray directions. For example, one embodiment of an apparatus comprises: An apparatus comprising: a ray generator to generate a plurality of rays; ray direction evaluation circuitry/logic to generate approximate ray direction data for each of the plurality of rays; ray sorting circuitry/logic to sort the rays into a plurality of ray queues based, at least in part, on the approximate ray direction data.
-
公开(公告)号：US20220157009A1
公开(公告)日：2022-05-19
申请号：US17533341
申请日：2021-11-23
申请人： INTEL CORPORATION
发明人： Karthik VAIDYANATHAN , Sven WOOP , Carsten BENTHIN
摘要： Apparatus and method for preventing re-traversal of a prior path on a restart. For example, one embodiment of an apparatus comprises: a ray generator to generate a plurality of rays in a graphics scene; a bounding volume hierarchy (BVH) generator to construct a BVH comprising a plurality of hierarchically arranged nodes, wherein the BVH comprises a specified number of child nodes at a current BVH level beneath a parent node in the hierarchy; circuitry to traverse one or more of the rays through the BVH to form a current traversal path and intersect the one or more rays with primitives contained within the nodes, wherein the circuitry is to process entries from the top of a first data structure comprising entries each associated with a child node at the current BVH level, the entries being ordered from top to bottom based on a sorted distance of each respective child node.
-
公开(公告)号：US20240104825A1
公开(公告)日：2024-03-28
申请号：US18376098
申请日：2023-10-03
申请人： INTEL CORPORATION
CPC分类号： G06T15/06 , G06T1/20 , G06T15/005 , G06T15/08 , G06T17/10
摘要： Apparatus and method for grouping rays based on quantized ray directions. For example, one embodiment of an apparatus comprises: An apparatus comprising: a ray generator to generate a plurality of rays; ray direction evaluation circuitry/logic to generate approximate ray direction data for each of the plurality of rays; ray sorting circuitry/logic to sort the rays into a plurality of ray queues based, at least in part, on the approximate ray direction data.
-
公开(公告)号：US20230298127A1
公开(公告)日：2023-09-21
申请号：US17699066
申请日：2022-03-18
申请人： Intel Corporation
发明人： Joshua Barczak , Sven WOOP , Pawel Majewski , Radoslaw DRABINSKI
CPC分类号： G06T1/60 , G06T15/06 , G06T15/10 , G06V10/44 , G06V10/761 , G06T2210/12 , G06T2210/21
摘要： Apparatus and method for a biased BVH traversal path. For example, one embodiment of an apparatus comprises: ray tracing traversal hardware logic to traverse a ray through nodes of a bounding volume hierarchy (BVH); and stack management hardware logic to push and pop entries on a traversal stack, each entry corresponding to a node of the BVH, wherein the ray tracing traversal hardware logic is to determine an order in which to push entries to the traversal stack based on both a first intersection value corresponding to a closest intersection point between the ray and a BVH node and a farthest intersection value between the ray and the BVH node. In addition, the ray traversal hardware logic may determine the order in which to push the entries to the traversal stack further based on a probability density value corresponding to a probability of a ray hitting geometry inside of the BVH.
-
公开(公告)号：US20220254090A1
公开(公告)日：2022-08-11
申请号：US17677118
申请日：2022-02-22
申请人： INTEL CORPORATION
发明人： Prasoonkumar SURTI , Carsten BENTHIN , Karthik VAIDYANATHAN , Philip LAWS , Scott JANUS , Sven WOOP
摘要： Cluster of acceleration engines to accelerate intersections. For example, one embodiment of an apparatus comprises: a set of graphics cores to execute a first set of instructions of a primary graphics thread; a scalar cluster comprising a plurality of scalar execution engines; and a communication fabric interconnecting the set of graphics cores and the scalar cluster; the set of graphics cores to offload execution of a second set of instructions associated with ray traversal and/or intersection operations to the scalar cluster; the scalar cluster comprising a plurality of local memories, each local memory associated with one of the scalar execution engines, wherein each local memory is to store a portion of a hierarchical acceleration data structure required by an associated scalar execution engine to execute one or more of the second set of instructions; the plurality of scalar execution engines to store results of the execution of the second set of instructions in a memory accessible by the set of graphics cores; wherein the set of graphics cores are to process the results within the primary graphics thread.
-
公开(公告)号：US20200320771A1
公开(公告)日：2020-10-08
申请号：US16786640
申请日：2020-02-10
申请人： Intel Corporation
摘要： Embodiments provide for a graphics processing apparatus including a graphics processing unit having bounding volume logic to operate on a compressed bounding volume hierarchy, wherein each bounding volume node stores a parent bounding volume and multiple child bounding volumes that are encoded relative to the parent bounding volume.
-
公开(公告)号：US20240265487A1
公开(公告)日：2024-08-08
申请号：US18433823
申请日：2024-02-06
申请人： Intel Corporation
发明人： Saikat MANDAL , Prasoonkumar SURTI , Sven WOOP
CPC分类号： G06T1/20 , G06F7/02 , G06F7/24 , G06F7/505 , G06F9/3885 , G06T15/005 , G06T15/08 , G06T17/10
摘要： Apparatus and method for stable and short latency sorting. For example, one embodiment of a processor comprises: an input circuit to receive a set of N input values to be sorted into a sorted order; comparison circuitry to compare each input value with all other input values in parallel to generate at least N*(N−1)/2 comparison result values; matrix generation circuitry and/or logic to generate a result matrix having a row associated with each input value, a plurality of bits in each row comprising comparison result values indicating results of comparisons with other input values, wherein a first region of the result matrix is to store a first set of bits comprising the N*(N−1)/2 comparison result values and a second region of the result matrix, opposite the first region, is to store a second set of bits comprising an inverse of the N*(N−1)/2 comparison result values; a parallel adder circuit to perform parallel additions of the bits in each row to generate N unique result values; and sorting circuitry to index into the N unique result values to return the sorted order.
-
公开(公告)号：US20240087208A1
公开(公告)日：2024-03-14
申请号：US18372783
申请日：2023-09-26
申请人： INTEL CORPORATION
发明人： Sven WOOP , Attila AFRA , Carsten BENTHIN , Ingo WALD , Johannes GUENTHER
CPC分类号： G06T15/005 , G06T1/20 , G06T15/06 , G06T17/00
摘要： A graphics processing apparatus comprising bounding volume hierarchy (BVH) construction circuitry to perform a spatial analysis and temporal analysis related to a plurality of input primitives and responsively generate a BVH comprising spatial, temporal, and spatial-temporal components that are hierarchically arranged, wherein the spatial components include a plurality of spatial nodes with children, the spatial nodes bounding the children using spatial bounds, and the temporal components comprise temporal nodes with children, the temporal nodes bounding their children using temporal bounds and the spatial-temporal components comprise spatial-temporal nodes with children, the spatial-temporal nodes bounding their children using spatial and temporal bounds; and ray traversal/intersection circuitry to traverse a ray or a set of rays through the BVH in accordance with the spatial and temporal components.
-
公开(公告)号：US20220366525A1
公开(公告)日：2022-11-17
申请号：US17707118
申请日：2022-03-29
申请人： INTEL CORPORATION
发明人： Carsten BENTHIN , Sven WOOP , Ingo WALD
摘要： Apparatus and method for compressing an acceleration data structure such as a bounding volume hierarchy (BVH). For example, one embodiment of a graphics processing apparatus comprises: one or more cores to execute graphics instructions including instructions to perform ray tracing operations; and compression circuitry to compress lowest level nodes of a hierarchical acceleration data structure comprising a plurality of hierarchically arranged nodes, each of the lowest level nodes comprising pointers to leaf data; the compression circuitry to quantize the lowest level nodes to generate quantized lowest level nodes and to store each quantized lowest level node and associated leaf data without the pointers to the leaf data.
-
-
-
-
-
-
-
-
-
搜索结果
21 条记录 (耗时 0.014 秒)
