公开(公告)号：US12118240B2

公开(公告)日：2024-10-15

申请号：US16987748

申请日：2020-08-07

Applicant: Intel Corporation

Inventor： Benjamin Walker ,  Sanjeev Trika ,  Kapil Karkra ,  James R. Harris ,  Steven C. Miller ,  Bishwajit Dutta

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0619 ,  G06F3/0656 ,  G06F3/0658 ,  G06F3/067 ,  G06F3/0689

Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to maintain a respective lookup table for each of two or more persistent storage devices in a persistent memory outside of the two or more persistent storage devices with a first indirection granularity that is smaller than a second indirection granularity of each of the two or more persistent storage devices, buffer write requests to the two or more persistent storage devices in the persistent memory in accordance with the respective lookup tables, and perform a sequential write from the persistent memory to a particular device of the two or more persistent storage devices when a portion of the buffer that corresponds to the particular device has an amount of data to write that corresponds to the second indirection granularity. Other embodiments are disclosed and claimed.

公开(公告)号：US20210405889A1

公开(公告)日：2021-12-30

申请号：US17470275

申请日：2021-09-09

Applicant: Intel Corporation

Inventor： Sanjeev Trika

IPC: G06F3/06 ,  G06F12/02 ,  G06F12/0891

Abstract: An embodiment of an electronic apparatus may comprise one or more substrates, and circuitry coupled to the one or more substrates, the circuitry to track transactions that access a first memory level of a multi-level memory, control access to at least the first memory level of the multi-level memory, and control a roll back of at least the first memory level of the multi-level memory based on the tracked transactions. In another embodiment, the circuitry is to control a roll back of a multi-level memory in response to a request to roll back the multi-level memory. Other embodiments are disclosed and claimed.

公开(公告)号：US20210389890A1

公开(公告)日：2021-12-16

申请号：US17459414

申请日：2021-08-27

Applicant: Intel Corporation

Inventor： Sanjeev Trika

IPC: G06F3/06

Abstract: Systems, apparatuses and methods may provide for memory controller technology that detects an application function, a data specifier associated with the application function, and one or more operating parameters associated with the application function, generates execution estimates for a plurality of computational storage devices based on the application function, the data specifier, the operating parameter(s), and one or more device capabilities associated with the plurality of computational storage devices, and selects a target storage device from the plurality of storage devices based on the execution estimates.

公开(公告)号：US10891233B2

公开(公告)日：2021-01-12

申请号：US16021677

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： Scott Burridge ,  William Chiu ,  Jawad Khan ,  Sanjeev Trika

IPC: G06F12/0866 ,  G06F12/0862

Abstract: Systems, apparatuses and methods may provide for technology to automatically identify a plurality of non-volatile memory locations associated with a file in response to a close operation with respect to the file and automatically conduct a prefetch from one or more of the plurality of non-volatile memory locations that have been most recently accessed and do not reference cached file segments. The prefetch may be conducted in response to an open operation with respect to the file and on a per-file segment basis.

公开(公告)号：US20190042232A1

公开(公告)日：2019-02-07

申请号：US16145701

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Sanjeev Trika

IPC: G06F8/75 ,  G06F8/41 ,  G06F9/50

Abstract: Technologies for automatic compilation of storage offloads include a compute device. The compute device further includes a compiler logic unit to analyze a source code of an application, identify a section of the source code that includes operations to be offloaded to a data storage device on a target compute device, extract, in response to an identification of the section that includes operations to be offloaded, the section of the source code, and compile the section of the source code extracted as an offload function.

公开(公告)号：US11074172B2

公开(公告)日：2021-07-27

申请号：US16244285

申请日：2019-01-10

Applicant: Intel Corporation

Inventor： Sanjeev Trika

IPC: G06F12/02 ,  G06F3/06 ,  G11C13/00

Abstract: An embodiment of a package apparatus may include technology to control a first persistent storage media of the electronic storage, control a second persistent storage media of the electronic storage, wherein the second persistent storage media includes one or more of a faster access time and a smaller granularity access as compared to the first persistent storage media, store a logical-to-physical table in the second persistent storage media, and, in response to a data copy command, update an entry in the logical-to-physical table corresponding to a destination logical block address for the data copy command to point to a same physical address as a source logical block address for the data copy command. Other embodiments are disclosed and claimed.

公开(公告)号：US10983729B2

公开(公告)日：2021-04-20

申请号：US16702382

申请日：2019-12-03

Applicant: Intel Corporation

Inventor： Jawad Basit Khan ,  Peng Li ,  Sanjeev Trika

IPC: G06F3/06 ,  G06F13/38 ,  G06F9/34

Abstract: In one embodiment, a storage device comprises non-volatile storage media; a controller to receive, from a host, an object definition command that identifies a first data object and a second data object and a transformation to apply to the first data object and the second data object to generate a first transformed object and store the first transformed object in the non-volatile storage media; and a transformation engine to apply the transformation to the first data object and the second data object.

公开(公告)号：US20200218474A1

公开(公告)日：2020-07-09

申请号：US16702382

申请日：2019-12-03

Applicant: Intel Corporation

Inventor： Jawad Basit Khan ,  Peng Li ,  Sanjeev Trika

IPC: G06F3/06 ,  G06F13/38 ,  G06F9/34

Abstract: In one embodiment, a storage device comprises non-volatile storage media; a controller to receive, from a host, an object definition command that identifies a first data object and a second data object and a transformation to apply to the first data object and the second data object to generate a first transformed object and store the first transformed object in the non-volatile storage media; and a transformation engine to apply the transformation to the first data object and the second data object.

公开(公告)号：US20200210207A1

公开(公告)日：2020-07-02

申请号：US16812026

申请日：2020-03-06

Applicant: Intel Corporation

Inventor： Sanjeev Trika

IPC: G06F9/4401 ,  G06F9/48 ,  G06F9/30 ,  G06F1/3221

Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to manage a persistent storage media, provide a host with an indication of a time for the host to initiate a subsequent wake-up for data management of the persistent storage media, and perform data management of the persistent storage media in response to a host-initiated wake-up from a zero power state. Other embodiments are disclosed and claimed.

公开(公告)号：US20190258504A1

公开(公告)日：2019-08-22

申请号：US16398017

申请日：2019-04-29

Applicant: Intel Corporation

Inventor： Sanjeev Trika ,  Bishwajit Dutta

IPC: G06F9/455 ,  G06F9/50 ,  G06F9/445

Abstract: Techniques and mechanisms for communicating compiled software instructions via a network, wherein the compiled instructions are to execute a kernel process of a network device. In an embodiment, a first node of a network receives a kernel source code from a second node of the network. The first node compiles the kernel source code to generate a kernel binary code, which is provided to the second node. Based on the kernel binary code being communicated to the second node, a software developer is able to perform a simulation that facilitates the development of an application binary code. The first node subsequently receives the application binary and an indication that the application binary is to be executed with the kernel binary at the first node. In some embodiments, the first node executes an application process and a kernel process to provide an application offload resource for another network node.