公开(公告)号：US11188467B2

公开(公告)日：2021-11-30

申请号：US15717939

申请日：2017-09-28

Applicant: Intel Corporation

Inventor： Israel Diamand ,  Alaa R. Alameldeen ,  Sreenivas Subramoney ,  Supratik Majumder ,  Srinivas Santosh Kumar Madugula ,  Jayesh Gaur ,  Zvika Greenfield ,  Anant V. Nori

IPC: G06F12/00 ,  G06F12/0846 ,  G06F12/0811 ,  G06F12/128 ,  G06F12/121 ,  G06F12/0886 ,  G06F12/08

Abstract: A method is described. The method includes receiving a read or write request for a cache line. The method includes directing the request to a set of logical super lines based on the cache line's system memory address. The method includes associating the request with a cache line of the set of logical super lines. The method includes, if the request is a write request: compressing the cache line to form a compressed cache line, breaking the cache line down into smaller data units and storing the smaller data units into a memory side cache. The method includes, if the request is a read request: reading smaller data units of the compressed cache line from the memory side cache and decompressing the cache line.

公开(公告)号：US20190213130A1

公开(公告)日：2019-07-11

申请号：US15863854

申请日：2018-01-05

Applicant: Intel Corporation

Inventor： Srinivas Santosh Kumar Madugula ,  Supratik Majumder

IPC: G06F12/0862 ,  G06F12/0811 ,  G06F12/0895 ,  G06F12/1045

CPC classification number: G06F12/0862 ,  G06F12/0811 ,  G06F12/0895 ,  G06F12/1045

Abstract: In one embodiment, a processor comprises a prefetcher comprising a plurality of trackers, a tracker of the plurality of trackers to store a prefetch mask to indicate which cache lines of a sector of a sectored cache have been prefetched from a system memory to the sectored cache; and a prefetch issuer comprising circuitry, the prefetch issuer to generate a prefetch request to prefetch cache lines of the sector of the sectored cache from the system memory into the sectored cache based on a prefetch confidence metric associated with the sector of the sectored cache.