公开(公告)号：US20210073047A1

公开(公告)日：2021-03-11

申请号：US16642563

申请日：2017-09-30

Applicant: INTEL CORPORATION

Inventor： Malini K. BHANDARU ,  Sundar NADATHUR ,  Joseph GRECCO ,  Roman DOBOSZ ,  Yongfeng DU

IPC: G06F9/50 ,  H04L12/24

Abstract: Technologies for managing accelerator resources include a cloud resource manager (102) to receive accelerator usage information from each of a plurality of node compute devices (104) and task parameters of a task to be performed. The cloud resource manager (102) accesses a task distribution policy, determines a destination node compute device (104) of the plurality of node compute devices (104) based on the task parameters and the task distribution policy, and assigns the task to the destination node compute device (104).

公开(公告)号：US20220113911A1

公开(公告)日：2022-04-14

申请号：US17558268

申请日：2021-12-21

Applicant: Intel Corporation

Inventor： Andrzej KURIATA ,  Susanne M. BALLE ,  Duane E. GALBI ,  Sundar NADATHUR ,  Nagabhushan CHITLUR ,  Francesc GUIM BERNAT ,  Alexander BACHMUTSKY

IPC: G06F3/06 ,  G06F15/78

Abstract: Methods, apparatus, and software for remote storage of hardware microservices hosted on other processing units (XPUs) and SOC-XPU Platforms. The apparatus may be a platform including a System on Chip (SOC) and an XPU, such as a Field Programmable Gate Array (FPGA). Software, via execution on the SOC, enables the platform to pre-provision storage space on a remote storage node and assign the storage space to the platform, wherein the pre-provisioned storage space includes one or more container images to be implemented as one or more hardware (HW) microservice front-ends. The XPU/FPGA is configured to implement one or more accelerator functions used to accelerate HW microservice backend operations that are offloaded from the one or more HW microservice front-ends. The platform is also configured to pre-provision a remote storage volume containing worker node components and access and persistently store worker node components.

公开(公告)号：US20220321434A1

公开(公告)日：2022-10-06

申请号：US17848898

申请日：2022-06-24

Applicant: Intel Corporation

Inventor： Andrzej KURIATA ,  Francesc GUIM BERNAT ,  Karthik KUMAR ,  Susanne M. BALLE ,  Alexander BACHMUTSKY ,  Duane E. GALBI ,  Nagabhushan CHITLUR ,  Sundar NADATHUR

IPC: H04L43/04 ,  G06F9/54 ,  H04L67/133 ,  H04L43/0852 ,  H04L67/51

Abstract: Reliability and performance of a data center is increased by processing telemetry data in a network device in the data center. A Telemetry Correlation Engine (TCE) in the network device correlates host level telemetry received from a compute node with low-level network device telemetry collected in the network device to identify performance bottlenecks for microservices based applications. The Telemetry Correlation Engine processes and analyzes the telemetry data from the compute node and network statistics available in the network device.

公开(公告)号：US20200174841A1

公开(公告)日：2020-06-04

申请号：US16619442

申请日：2017-06-29

Applicant: INTEL CORPORATION

Inventor： Pratik M. MAROLIA ,  Aaron J. GRIER ,  Henry M. MITCHEL ,  Joseph GRECCO ,  Michael C. ADLER ,  Utkarsh Y. KAKAIYA ,  Joshua D. FENDER ,  Sundar NADATHUR ,  Nagabhushan CHITLUR

IPC: G06F9/50 ,  G06F9/46 ,  G06F9/48

Abstract: A system comprising an accelerator circuit comprising an accelerator function unit to implement a first function, and one or more device feature header (DFH) circuits to provide attributes associated with the accelerator function unit, and a processor to retrieve the attributes of the accelerator function unit by traversing a device feature list (DFL) referencing the one or more DFH circuits, execute, based on the attributes, an application encoding the first function to cause the accelerator function unit to perform the first function.

公开(公告)号：US20230185760A1

公开(公告)日：2023-06-15

申请号：US17549727

申请日：2021-12-13

Applicant: Intel Corporation

Inventor： Susanne M. BALLE ,  Duane E. GALBI ,  Andrzej KURIATA ,  Sundar NADATHUR ,  Nagabhushan CHITLUR ,  Francesc GUIM BERNAT ,  Alexander BACHMUTSKY

IPC: G06F15/78

CPC classification number: G06F15/7889 ,  G06F15/7821 ,  G06F15/7871 ,  G06F2015/768

Abstract: Methods, apparatus, and software and for hardware microservices accelerated in other processing units (XPUs). The apparatus may be a platform including a System on Chip (SOC) and an XPU, such as a Field Programmable Gate Array (FPGA). The FPGA is configured to implement one or more Hardware (HW) accelerator functions associated with HW microservices. Execution of microservices is split between a software front-end that executes on the SOC and a hardware backend comprising the HW accelerator functions. The software front-end offloads a portion of a microservice and/or associated workload to the HW microservice backend implemented by the accelerator functions. An XPU or FPGA proxy is used to provide the microservice front-ends with shared access to HW accelerator functions, and schedules/multiplexes access to the HW accelerator functions using, e.g., telemetry data generated by the microservice front-ends and/or the HW accelerator functions. The platform may be an infrastructure processing unit (IPU) configured to accelerate infrastructure operations.

公开(公告)号：US20230070995A1

公开(公告)日：2023-03-09

申请号：US17884244

申请日：2022-08-09

Applicant: Intel Corporation

Inventor： Pratik M. MAROLIA ,  Aaron J. GRIER ,  Henry M. MITCHEL ,  Joseph GRECCO ,  Michael C. ADLER ,  Utkarsh Y. KAKAIYA ,  Joshua D. FENDER ,  Sundar NADATHUR ,  Nagabhushan CHITLUR

IPC: G06F9/50 ,  G06F9/46 ,  G06F9/48

Abstract: A system comprising an accelerator circuit comprising an accelerator function unit to implement a first function, and one or more device feature header (DFH) circuits to provide attributes associated with the accelerator function unit, and a processor to retrieve the attributes of the accelerator function unit by traversing a device feature list (DFL) referencing the one or more DFH circuits, execute, based on the attributes, an application encoding the first function to cause the accelerator function unit to perform the first function.

公开(公告)号：US20220206864A1

公开(公告)日：2022-06-30

申请号：US17694516

申请日：2022-03-14

Applicant: Intel Corporation

Inventor： Sundar NADATHUR ,  Susanne M. BALLE ,  Andrzej KURIATA ,  Duane E. GALBI ,  Nagabhushan CHITLUR ,  Francesc GUIM BERNAT ,  Alexander BACHMUTSKY

IPC: G06F9/50 ,  G06F8/65

Abstract: Examples described herein relate to causing execution of a workload on a device based on characteristics of the device and based on metadata associated with the device identifying execution requirements and software and hardware compatibilities between the device and a platform environment. In some examples, an accelerator device is selected to execute a workload based on characteristics of the accelerator device and based on software and hardware compatibilities between the device and a platform environment of the accelerator device.